diff --git a/neon_intrinsics/advsimd.md b/neon_intrinsics/advsimd.md
index e8ceab6d..98cf28d0 100644
--- a/neon_intrinsics/advsimd.md
+++ b/neon_intrinsics/advsimd.md
@@ -2620,10 +2620,6 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>int64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128" target="_blank">vreinterpretq_s64_p128</a>(poly128_t a)</code>    | `a -> Vd.1Q`           | `NOP`                 | `Vd.2D -> result`  | `A32/A64`                 |
 | <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128" target="_blank">vreinterpretq_f64_p128</a>(poly128_t a)</code>  | `a -> Vd.1Q`           | `NOP`                 | `Vd.2D -> result`  | `A64`                     |
 | <code>float16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128" target="_blank">vreinterpretq_f16_p128</a>(poly128_t a)</code>  | `a -> Vd.1Q`           | `NOP`                 | `Vd.8H -> result`  | `A32/A64`                 |
-| <code>mfloat8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_mf8_u8" target="_blank">vreinterpret_mf8_u8</a>(uint8x8_t a)</code>        | `a -> Vd.8B`           | `NOP`                 | `Vd.8B -> result`  | `A64`                     |
-| <code>mfloat8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_mf8_u8" target="_blank">vreinterpretq_mf8_u8</a>(uint8x16_t a)</code>    | `a -> Vd.16B`          | `NOP`                 | `Vd.16B -> result` | `A64`                     |
-| <code>uint8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_mf8" target="_blank">vreinterpret_u8_mf8</a>(mfloat8x8_t a)</code>        | `a -> Vd.8B`           | `NOP`                 | `Vd.8B -> result`  | `A64`                     |
-| <code>uint8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_mf8" target="_blank">vreinterpretq_u8_mf8</a>(mfloat8x16_t a)</code>    | `a -> Vd.16B`          | `NOP`                 | `Vd.16B -> result` | `A64`                     |
 
 ### Move
 
@@ -3250,7 +3246,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>int16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16" target="_blank">vdupq_n_s16</a>(int16_t value)</code>                                                                                        | `value -> rn`                        | `DUP Vd.8H,rn`          | `Vd.8H -> result`  | `v7/A32/A64`              |
 | <code>int32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32" target="_blank">vdup_n_s32</a>(int32_t value)</code>                                                                                          | `value -> rn`                        | `DUP Vd.2S,rn`          | `Vd.2S -> result`  | `v7/A32/A64`              |
 | <code>int32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32" target="_blank">vdupq_n_s32</a>(int32_t value)</code>                                                                                        | `value -> rn`                        | `DUP Vd.4S,rn`          | `Vd.4S -> result`  | `v7/A32/A64`              |
-| <code>int64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64" target="_blank">vdup_n_s64</a>(int64_t value)</code>                                                                                          | `value -> rn`                        | `INS Dd.D[0],xn`        | `Vd.1D -> result`  | `v7/A32/A64`              |
+| <code>int64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64" target="_blank">vdup_n_s64</a>(int64_t value)</code>                                                                                          | `value -> Xn`                        | `FMOV Dd,Xn`            | `Vd.1D -> result`  | `v7/A32/A64`              |
 | <code>int64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64" target="_blank">vdupq_n_s64</a>(int64_t value)</code>                                                                                        | `value -> rn`                        | `DUP Vd.2D,rn`          | `Vd.2D -> result`  | `v7/A32/A64`              |
 | <code>uint8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8" target="_blank">vdup_n_u8</a>(uint8_t value)</code>                                                                                            | `value -> rn`                        | `DUP Vd.8B,rn`          | `Vd.8B -> result`  | `v7/A32/A64`              |
 | <code>uint8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8" target="_blank">vdupq_n_u8</a>(uint8_t value)</code>                                                                                         | `value -> rn`                        | `DUP Vd.16B,rn`         | `Vd.16B -> result` | `v7/A32/A64`              |
@@ -3258,9 +3254,9 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>uint16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16" target="_blank">vdupq_n_u16</a>(uint16_t value)</code>                                                                                      | `value -> rn`                        | `DUP Vd.8H,rn`          | `Vd.8H -> result`  | `v7/A32/A64`              |
 | <code>uint32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32" target="_blank">vdup_n_u32</a>(uint32_t value)</code>                                                                                        | `value -> rn`                        | `DUP Vd.2S,rn`          | `Vd.2S -> result`  | `v7/A32/A64`              |
 | <code>uint32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32" target="_blank">vdupq_n_u32</a>(uint32_t value)</code>                                                                                      | `value -> rn`                        | `DUP Vd.4S,rn`          | `Vd.4S -> result`  | `v7/A32/A64`              |
-| <code>uint64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64" target="_blank">vdup_n_u64</a>(uint64_t value)</code>                                                                                        | `value -> rn`                        | `INS Dd.D[0],xn`        | `Vd.1D -> result`  | `v7/A32/A64`              |
+| <code>uint64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64" target="_blank">vdup_n_u64</a>(uint64_t value)</code>                                                                                        | `value -> Xn`                        | `FMOV Dd,Xn`            | `Vd.1D -> result`  | `v7/A32/A64`              |
 | <code>uint64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u64" target="_blank">vdupq_n_u64</a>(uint64_t value)</code>                                                                                      | `value -> rn`                        | `DUP Vd.2D,rn`          | `Vd.2D -> result`  | `v7/A32/A64`              |
-| <code>poly64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p64" target="_blank">vdup_n_p64</a>(poly64_t value)</code>                                                                                        | `value -> rn`                        | `INS Dd.D[0],xn`        | `Vd.1D -> result`  | `A32/A64`                 |
+| <code>poly64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p64" target="_blank">vdup_n_p64</a>(poly64_t value)</code>                                                                                        | `value -> Xn`                        | `FMOV Dd,Xn`            | `Vd.1D -> result`  | `A32/A64`                 |
 | <code>poly64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p64" target="_blank">vdupq_n_p64</a>(poly64_t value)</code>                                                                                      | `value -> rn`                        | `DUP Vd.2D,rn`          | `Vd.2D -> result`  | `A32/A64`                 |
 | <code>float32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32" target="_blank">vdup_n_f32</a>(float32_t value)</code>                                                                                      | `value -> rn`                        | `DUP Vd.2S,rn`          | `Vd.2S -> result`  | `v7/A32/A64`              |
 | <code>float32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32" target="_blank">vdupq_n_f32</a>(float32_t value)</code>                                                                                    | `value -> rn`                        | `DUP Vd.4S,rn`          | `Vd.4S -> result`  | `v7/A32/A64`              |
@@ -3268,7 +3264,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>poly8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p8" target="_blank">vdupq_n_p8</a>(poly8_t value)</code>                                                                                         | `value -> rn`                        | `DUP Vd.16B,rn`         | `Vd.16B -> result` | `v7/A32/A64`              |
 | <code>poly16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p16" target="_blank">vdup_n_p16</a>(poly16_t value)</code>                                                                                        | `value -> rn`                        | `DUP Vd.4H,rn`          | `Vd.4H -> result`  | `v7/A32/A64`              |
 | <code>poly16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p16" target="_blank">vdupq_n_p16</a>(poly16_t value)</code>                                                                                      | `value -> rn`                        | `DUP Vd.8H,rn`          | `Vd.8H -> result`  | `v7/A32/A64`              |
-| <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f64" target="_blank">vdup_n_f64</a>(float64_t value)</code>                                                                                      | `value -> rn`                        | `INS Dd.D[0],xn`        | `Vd.1D -> result`  | `A64`                     |
+| <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f64" target="_blank">vdup_n_f64</a>(float64_t value)</code>                                                                                      | `value -> Xn`                        | `FMOV Dd,Xn`            | `Vd.1D -> result`  | `A64`                     |
 | <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f64" target="_blank">vdupq_n_f64</a>(float64_t value)</code>                                                                                    | `value -> rn`                        | `DUP Vd.2D,rn`          | `Vd.2D -> result`  | `A64`                     |
 | <code>mfloat8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_mf8" target="_blank">vdup_n_mf8</a>(mfloat8_t value)</code>                                                                                      | `value -> rn`                        | `DUP Vd.8B,rn`          | `Vd.8B -> result`  | `A64`                     |
 | <code>mfloat8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_mf8" target="_blank">vdupq_n_mf8</a>(mfloat8_t value)</code>                                                                                   | `value -> rn`                        | `DUP Vd.16B,rn`         | `Vd.16B -> result` | `A64`                     |
@@ -3324,7 +3320,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
 | <code>poly16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16" target="_blank">vdupq_lane_p16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; poly16x4_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code>       | `vec -> Vn.4H`<br>`0 <= lane <= 3`   | `DUP Vd.8H,Vn.H[lane]`  | `Vd.8H -> result`  | `v7/A32/A64`              |
 | <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64" target="_blank">vdup_lane_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code>       | `vec -> Vn.1D`<br>`0 <= lane <= 0`   | `DUP Dd,Vn.D[lane]`     | `Dd -> result`     | `A64`                     |
 | <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64" target="_blank">vdupq_lane_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code>     | `vec -> Vn.1D`<br>`0 <= lane <= 0`   | `DUP Vd.2D,Vn.D[lane]`  | `Vd.2D -> result`  | `A64`                     |
-| <code>mfloat8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_mf8" target="_blank">vdup_lane_mf8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; mfloat8x8_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code>       | `vec -> Vn.8B`<br>`0 <= lane <= 7`   | `DUP Vd.8B,Vn.B[lane]`  | `Vd.8B -> result`  | `/A64`                    |
+| <code>mfloat8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_mf8" target="_blank">vdup_lane_mf8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; mfloat8x8_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code>       | `vec -> Vn.8B`<br>`0 <= lane <= 7`   | `DUP Vd.8B,Vn.B[lane]`  | `Vd.8B -> result`  | `A64`                     |
 | <code>mfloat8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_mf8" target="_blank">vdupq_lane_mf8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; mfloat8x8_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code>    | `vec -> Vn.8B`<br>`0 <= lane <= 7`   | `DUP Vd.16B,Vn.B[lane]` | `Vd.16B -> result` | `A64`                     |
 | <code>int8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8" target="_blank">vdup_laneq_s8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int8x16_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code>            | `vec -> Vn.16B`<br>`0 <= lane <= 15` | `DUP Vd.8B,Vn.B[lane]`  | `Vd.8B -> result`  | `A64`                     |
 | <code>int8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8" target="_blank">vdupq_laneq_s8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int8x16_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code>         | `vec -> Vn.16B`<br>`0 <= lane <= 15` | `DUP Vd.16B,Vn.B[lane]` | `Vd.16B -> result` | `A64`                     |
diff --git a/tools/intrinsic_db/advsimd.csv b/tools/intrinsic_db/advsimd.csv
index 561eee02..2f2ef3b1 100644
--- a/tools/intrinsic_db/advsimd.csv
+++ b/tools/intrinsic_db/advsimd.csv
@@ -1923,7 +1923,7 @@ int16x4_t vdup_n_s16(int16_t value)	value -> rn	DUP Vd.4H,rn	Vd.4H -> result	v7/
 int16x8_t vdupq_n_s16(int16_t value)	value -> rn	DUP Vd.8H,rn	Vd.8H -> result	v7/A32/A64
 int32x2_t vdup_n_s32(int32_t value)	value -> rn	DUP Vd.2S,rn	Vd.2S -> result	v7/A32/A64
 int32x4_t vdupq_n_s32(int32_t value)	value -> rn	DUP Vd.4S,rn	Vd.4S -> result	v7/A32/A64
-int64x1_t vdup_n_s64(int64_t value)	value -> rn	INS Dd.D[0],xn	Vd.1D -> result	v7/A32/A64
+int64x1_t vdup_n_s64(int64_t value)	value -> Xn	FMOV Dd,Xn	Vd.1D -> result	v7/A32/A64
 int64x2_t vdupq_n_s64(int64_t value)	value -> rn	DUP Vd.2D,rn	Vd.2D -> result	v7/A32/A64
 uint8x8_t vdup_n_u8(uint8_t value)	value -> rn	DUP Vd.8B,rn	Vd.8B -> result	v7/A32/A64
 uint8x16_t vdupq_n_u8(uint8_t value)	value -> rn	DUP Vd.16B,rn	Vd.16B -> result	v7/A32/A64
@@ -1931,9 +1931,9 @@ uint16x4_t vdup_n_u16(uint16_t value)	value -> rn	DUP Vd.4H,rn	Vd.4H -> result	v
 uint16x8_t vdupq_n_u16(uint16_t value)	value -> rn	DUP Vd.8H,rn	Vd.8H -> result	v7/A32/A64
 uint32x2_t vdup_n_u32(uint32_t value)	value -> rn	DUP Vd.2S,rn	Vd.2S -> result	v7/A32/A64
 uint32x4_t vdupq_n_u32(uint32_t value)	value -> rn	DUP Vd.4S,rn	Vd.4S -> result	v7/A32/A64
-uint64x1_t vdup_n_u64(uint64_t value)	value -> rn	INS Dd.D[0],xn	Vd.1D -> result	v7/A32/A64
+uint64x1_t vdup_n_u64(uint64_t value)	value -> Xn	FMOV Dd,Xn	Vd.1D -> result	v7/A32/A64
 uint64x2_t vdupq_n_u64(uint64_t value)	value -> rn	DUP Vd.2D,rn	Vd.2D -> result	v7/A32/A64
-poly64x1_t vdup_n_p64(poly64_t value)	value -> rn	INS Dd.D[0],xn	Vd.1D -> result	A32/A64
+poly64x1_t vdup_n_p64(poly64_t value)	value -> Xn	FMOV Dd,Xn	Vd.1D -> result	A32/A64
 poly64x2_t vdupq_n_p64(poly64_t value)	value -> rn	DUP Vd.2D,rn	Vd.2D -> result	A32/A64
 float32x2_t vdup_n_f32(float32_t value)	value -> rn	DUP Vd.2S,rn	Vd.2S -> result	v7/A32/A64
 float32x4_t vdupq_n_f32(float32_t value)	value -> rn	DUP Vd.4S,rn	Vd.4S -> result	v7/A32/A64
@@ -1941,7 +1941,7 @@ poly8x8_t vdup_n_p8(poly8_t value)	value -> rn	DUP Vd.8B,rn	Vd.8B -> result	v7/A
 poly8x16_t vdupq_n_p8(poly8_t value)	value -> rn	DUP Vd.16B,rn	Vd.16B -> result	v7/A32/A64
 poly16x4_t vdup_n_p16(poly16_t value)	value -> rn	DUP Vd.4H,rn	Vd.4H -> result	v7/A32/A64
 poly16x8_t vdupq_n_p16(poly16_t value)	value -> rn	DUP Vd.8H,rn	Vd.8H -> result	v7/A32/A64
-float64x1_t vdup_n_f64(float64_t value)	value -> rn	INS Dd.D[0],xn	Vd.1D -> result	A64
+float64x1_t vdup_n_f64(float64_t value)	value -> Xn	FMOV Dd,Xn	Vd.1D -> result	A64
 float64x2_t vdupq_n_f64(float64_t value)	value -> rn	DUP Vd.2D,rn	Vd.2D -> result	A64
 mfloat8x8_t vdup_n_mf8(mfloat8_t value)	value -> rn	DUP Vd.8B,rn	Vd.8B -> result	A64
 mfloat8x16_t vdupq_n_mf8(mfloat8_t value)	value -> rn	DUP Vd.16B,rn	Vd.16B -> result	A64
@@ -1997,7 +1997,7 @@ poly16x4_t vdup_lane_p16(poly16x4_t vec, __builtin_constant_p(lane))	vec -> Vn.4
 poly16x8_t vdupq_lane_p16(poly16x4_t vec, __builtin_constant_p(lane))	vec -> Vn.4H;0 <= lane <= 3	DUP Vd.8H,Vn.H[lane]	Vd.8H -> result	v7/A32/A64
 float64x1_t vdup_lane_f64(float64x1_t vec, __builtin_constant_p(lane))	vec -> Vn.1D;0 <= lane <= 0	DUP Dd,Vn.D[lane]	Dd -> result	A64
 float64x2_t vdupq_lane_f64(float64x1_t vec, __builtin_constant_p(lane))	vec -> Vn.1D;0 <= lane <= 0	DUP Vd.2D,Vn.D[lane]	Vd.2D -> result	A64
-mfloat8x8_t vdup_lane_mf8(mfloat8x8_t vec, __builtin_constant_p(lane))	vec -> Vn.8B;0 <= lane <= 7	DUP Vd.8B,Vn.B[lane]	Vd.8B -> result	/A64
+mfloat8x8_t vdup_lane_mf8(mfloat8x8_t vec, __builtin_constant_p(lane))	vec -> Vn.8B;0 <= lane <= 7	DUP Vd.8B,Vn.B[lane]	Vd.8B -> result	A64
 mfloat8x16_t vdupq_lane_mf8(mfloat8x8_t vec, __builtin_constant_p(lane))	vec -> Vn.8B;0 <= lane <= 7	DUP Vd.16B,Vn.B[lane]	Vd.16B -> result	A64
 int8x8_t vdup_laneq_s8(int8x16_t vec, __builtin_constant_p(lane))	vec -> Vn.16B;0 <= lane <= 15	DUP Vd.8B,Vn.B[lane]	Vd.8B -> result	A64
 int8x16_t vdupq_laneq_s8(int8x16_t vec, __builtin_constant_p(lane))	vec -> Vn.16B;0 <= lane <= 15	DUP Vd.16B,Vn.B[lane]	Vd.16B -> result	A64
@@ -3928,10 +3928,6 @@ uint64x2_t vreinterpretq_u64_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.2D -> result	A3
 int64x2_t vreinterpretq_s64_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.2D -> result	A32/A64
 float64x2_t vreinterpretq_f64_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.2D -> result	A64
 float16x8_t vreinterpretq_f16_p128(poly128_t a)	a -> Vd.1Q	NOP	Vd.8H -> result	A32/A64
-mfloat8x8_t vreinterpret_mf8_u8(uint8x8_t a)	a -> Vd.8B	NOP	Vd.8B -> result	A64
-mfloat8x16_t vreinterpretq_mf8_u8(uint8x16_t a)	a -> Vd.16B	NOP	Vd.16B -> result	A64
-uint8x8_t vreinterpret_u8_mf8(mfloat8x8_t a)	a -> Vd.8B	NOP	Vd.8B -> result	A64
-uint8x16_t vreinterpretq_u8_mf8(mfloat8x16_t a)	a -> Vd.16B	NOP	Vd.16B -> result	A64
 poly128_t vldrq_p128(poly128_t const *ptr)	ptr -> Xn	LDR Qd,[Xn]	Qd -> result	A32/A64
 void vstrq_p128(poly128_t *ptr, poly128_t val)	val -> Qt;ptr -> Xn	STR Qt,[Xn]		A32/A64