From c871987722b55ca2f7983fb82a8da702537812db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 21:14:40 +0200 Subject: [PATCH 01/28] build: add bazel-orfs beta test for design builds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds Bazel-based design builds via bazel-orfs as a beta test alongside the existing Make flow. Lets users build ORFS designs with Bazel using the same config.mk files. Key changes: - MODULE.bazel: pin bazel-orfs at 78f19f25cec7 with yosys-slang plugin for slang HDL frontend; pin tools/OpenROAD via local_path_override. - flow/scripts/variables.yaml: register LIB_MODEL, MIN_CLK_ROUTING_LAYER, SDC_FILE_EXTRA, SYNTH_NUM_PARTITIONS, MOCK_ALU_OPERATIONS, MOCK_ALU_WIDTH so designs that use them pass bazel-orfs variable validation. - flow/designs/**/BUILD.bazel: add orfs_design() entry points for all public-PDK designs across asap7, sky130hd, sky130hs, nangate45, gf180, ihp-sg13g2. - flow/designs/src/**/BUILD.bazel: filegroup/exports_files for design source trees referenced via VERILOG_FILES. - flow/scripts/run_command.py: strip Bazel runfiles env vars before spawning subprocesses so child make invocations don't inherit them. - bazel-orfs.md: usage documentation, target conventions, working/blocked designs, and known limitations. Bumps tools/OpenROAD submodule to latest origin/master (26Q2-876-g45b7772b73) for the openroad/qt-bazel/yosys-slang integration that the new bazel-orfs relies on. Signed-off-by: Øyvind Harboe --- .bazelrc | 2 + MODULE.bazel | 89 +- MODULE.bazel.lock | 8064 +++++++++-------- bazel-orfs.md | 292 + flow/BUILD.bazel | 30 +- flow/designs/BUILD.bazel | 1 + flow/designs/asap7/aes-block/BUILD.bazel | 6 + flow/designs/asap7/aes-mbff/BUILD.bazel | 6 + flow/designs/asap7/aes/BUILD.bazel | 6 + flow/designs/asap7/aes_lvt/BUILD.bazel | 6 + flow/designs/asap7/cva6/BUILD.bazel | 7 + flow/designs/asap7/ethmac/BUILD.bazel | 6 + flow/designs/asap7/ethmac_lvt/BUILD.bazel | 6 + flow/designs/asap7/gcd-ccs/BUILD.bazel | 6 + flow/designs/asap7/gcd/BUILD.bazel | 6 + flow/designs/asap7/ibex/BUILD.bazel | 7 + flow/designs/asap7/jpeg/BUILD.bazel | 7 + flow/designs/asap7/jpeg_lvt/BUILD.bazel | 7 + flow/designs/asap7/minimal/BUILD.bazel | 7 + flow/designs/asap7/mock-alu/BUILD.bazel | 6 + flow/designs/asap7/mock-cpu/BUILD.bazel | 7 + .../asap7/riscv32i-mock-sram/BUILD.bazel | 7 + .../fakeram7_256x32/BUILD.bazel | 6 + flow/designs/asap7/riscv32i/BUILD.bazel | 7 + flow/designs/asap7/swerv_wrapper/BUILD.bazel | 7 + .../asap7/swerv_wrapper/lef/BUILD.bazel | 10 + .../asap7/swerv_wrapper/lib/BUILD.bazel | 10 + flow/designs/asap7/uart/BUILD.bazel | 7 + flow/designs/gf180/aes-hybrid/BUILD.bazel | 7 + flow/designs/gf180/aes-hybrid/rules-base.json | 24 +- flow/designs/gf180/aes/BUILD.bazel | 7 + flow/designs/gf180/ibex/BUILD.bazel | 7 + flow/designs/gf180/jpeg/BUILD.bazel | 7 + flow/designs/gf180/riscv32i/BUILD.bazel | 7 + flow/designs/gf180/uart-blocks/BUILD.bazel | 6 + .../designs/gf180/uart-blocks/rules-base.json | 42 +- .../gf180/uart-blocks/uart_rx/BUILD.bazel | 6 + flow/designs/ihp-sg13g2/aes/BUILD.bazel | 7 + flow/designs/ihp-sg13g2/gcd/BUILD.bazel | 7 + .../ihp-sg13g2/i2c-gpio-expander/BUILD.bazel | 6 + .../I2cDeviceCtrl/BUILD.bazel | 6 + flow/designs/ihp-sg13g2/ibex/BUILD.bazel | 7 + flow/designs/ihp-sg13g2/jpeg/BUILD.bazel | 7 + flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel | 7 + flow/designs/ihp-sg13g2/spi/BUILD.bazel | 7 + flow/designs/nangate45/aes/BUILD.bazel | 7 + flow/designs/nangate45/ariane133/BUILD.bazel | 6 + flow/designs/nangate45/ariane136/BUILD.bazel | 6 + .../nangate45/ariane136/rules-base.json | 46 +- .../nangate45/black_parrot/BUILD.bazel | 6 + flow/designs/nangate45/bp_be_top/BUILD.bazel | 6 + .../nangate45/bp_be_top/rules-base.json | 34 +- flow/designs/nangate45/bp_fe_top/BUILD.bazel | 6 + .../nangate45/bp_multi_top/BUILD.bazel | 6 + flow/designs/nangate45/bp_quad/BUILD.bazel | 6 + .../nangate45/dynamic_node/BUILD.bazel | 7 + flow/designs/nangate45/gcd/BUILD.bazel | 7 + flow/designs/nangate45/ibex/BUILD.bazel | 7 + flow/designs/nangate45/jpeg/BUILD.bazel | 7 + .../nangate45/mempool_group/BUILD.bazel | 6 + flow/designs/nangate45/swerv/BUILD.bazel | 7 + .../nangate45/swerv_wrapper/BUILD.bazel | 6 + flow/designs/nangate45/tinyRocket/BUILD.bazel | 7 + flow/designs/sky130hd/aes/BUILD.bazel | 6 + flow/designs/sky130hd/chameleon/BUILD.bazel | 7 + .../sky130hd/chameleon/gds/BUILD.bazel | 10 + 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flow/designs/src/mempool_group/BUILD.bazel | 10 + .../designs/src/mempool_group/rtl/BUILD.bazel | 16 + .../src/mempool_group/rtl/axi/BUILD.bazel | 4 + .../src/mempool_group/rtl/axi/src/BUILD.bazel | 4 + .../rtl/cluster_interconnect/BUILD.bazel | 4 + .../rtl/cluster_interconnect/rtl/BUILD.bazel | 4 + .../rtl/tcdm_interconnect/BUILD.bazel | 4 + .../variable_latency_interconnect/BUILD.bazel | 4 + .../rtl/common_cells/BUILD.bazel | 4 + .../rtl/common_cells/src/BUILD.bazel | 4 + .../common_cells/src/deprecated/BUILD.bazel | 4 + .../src/mempool_group/rtl/mempool/BUILD.bazel | 4 + .../rtl/register_interface/BUILD.bazel | 4 + .../register_interface/include/BUILD.bazel | 13 + .../include/register_interface/BUILD.bazel | 4 + .../src/mempool_group/rtl/snitch/BUILD.bazel | 4 + .../mempool_group/rtl/snitch/src/BUILD.bazel | 4 + .../rtl/snitch/src/snitch_icache/BUILD.bazel | 4 + .../rtl/tech_cells_generic/BUILD.bazel | 4 + .../rtl/tech_cells_generic/src/BUILD.bazel | 4 + .../tech_cells_generic/src/rtl/BUILD.bazel | 4 + flow/designs/src/microwatt/BUILD.bazel | 10 + flow/designs/src/microwatt/IPs/BUILD.bazel | 16 + flow/designs/src/mock-alu/BUILD.bazel | 10 + flow/designs/src/mock-array/BUILD.bazel | 4 + flow/designs/src/riscv32i/BUILD.bazel | 10 + flow/designs/src/spi/BUILD.bazel | 10 + flow/designs/src/swerv/BUILD.bazel | 10 + flow/designs/src/tinyRocket/BUILD.bazel | 10 + flow/designs/src/uart-no-param/BUILD.bazel | 10 + flow/designs/src/uart/BUILD.bazel | 10 + flow/scripts/variables.yaml | 52 + 180 files changed, 6022 insertions(+), 4013 deletions(-) create mode 100644 bazel-orfs.md create mode 100644 flow/designs/BUILD.bazel create mode 100644 flow/designs/asap7/aes-block/BUILD.bazel create mode 100644 flow/designs/asap7/aes-mbff/BUILD.bazel create mode 100644 flow/designs/asap7/aes/BUILD.bazel create mode 100644 flow/designs/asap7/aes_lvt/BUILD.bazel create mode 100644 flow/designs/asap7/cva6/BUILD.bazel create mode 100644 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flow/designs/src/jpeg/BUILD.bazel create mode 100644 flow/designs/src/jpeg/include/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/axi/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/axi/src/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/cluster_interconnect/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/common_cells/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/common_cells/src/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/mempool/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/register_interface/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/register_interface/include/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/snitch/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/snitch/src/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/tech_cells_generic/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/tech_cells_generic/src/BUILD.bazel create mode 100644 flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/BUILD.bazel create mode 100644 flow/designs/src/microwatt/BUILD.bazel create mode 100644 flow/designs/src/microwatt/IPs/BUILD.bazel create mode 100644 flow/designs/src/mock-alu/BUILD.bazel create mode 100644 flow/designs/src/mock-array/BUILD.bazel create mode 100644 flow/designs/src/riscv32i/BUILD.bazel create mode 100644 flow/designs/src/spi/BUILD.bazel create mode 100644 flow/designs/src/swerv/BUILD.bazel create mode 100644 flow/designs/src/tinyRocket/BUILD.bazel create mode 100644 flow/designs/src/uart-no-param/BUILD.bazel create mode 100644 flow/designs/src/uart/BUILD.bazel diff --git a/.bazelrc b/.bazelrc index b1d0bd32db..2a3ecca931 100644 --- a/.bazelrc +++ b/.bazelrc @@ -1,2 +1,4 @@ build --incompatible_strict_action_env +common --experimental_isolated_extension_usages +build --cxxopt "-std=c++20" --host_cxxopt "-std=c++20" try-import %workspace%/user.bazelrc diff --git a/MODULE.bazel b/MODULE.bazel index 227f8f7f3d..97b040762f 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -5,17 +5,67 @@ module( version = "0.0.1", ) +# --- Regular dependencies --- + +bazel_dep(name = "rules_python", version = "1.8.5") +bazel_dep(name = "rules_shell", version = "0.6.1") +bazel_dep(name = "toolchains_llvm", version = "1.5.0") + +bazel_dep(name = "openroad") +local_path_override( + module_name = "openroad", + path = "tools/OpenROAD", +) + +bazel_dep(name = "qt-bazel") +git_override( + module_name = "qt-bazel", + commit = "886104974c2fd72439f2c33b5deebf0fe4649df7", + remote = "https://github.com/The-OpenROAD-Project/qt_bazel_prebuilts", +) + bazel_dep(name = "bazel-orfs") +bazel_dep(name = "bazel-orfs-verilog") + +BAZEL_ORFS_COMMIT = "78f19f25cec73bdec3517a76465dec7ce17ce227" + +BAZEL_ORFS_REMOTE = "https://github.com/The-OpenROAD-Project/bazel-orfs.git" # To bump version, run: bazelisk run @bazel-orfs//:bump git_override( module_name = "bazel-orfs", - commit = "f8a4b694b37c8f5322323eba9a9ae37f9541ee17", - remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git", + commit = BAZEL_ORFS_COMMIT, + remote = BAZEL_ORFS_REMOTE, ) -bazel_dep(name = "rules_python", version = "1.8.5") -bazel_dep(name = "rules_shell", version = "0.6.1") +git_override( + module_name = "bazel-orfs-verilog", + commit = BAZEL_ORFS_COMMIT, + remote = BAZEL_ORFS_REMOTE, + strip_prefix = "verilog", +) + +# yosys-slang is not on BCR. Pin to a commit on povik/yosys-slang master +# that has the upstream Bazel build (povik/yosys-slang#310) and the +# slang.so visibility fix (povik/yosys-slang#311). Submodules pull in +# vendored slang and fmt sources. +bazel_dep(name = "yosys-slang") +git_override( + module_name = "yosys-slang", + commit = "7753ea70431d85929292b90c33b32f6dbdb3b048", + init_submodules = True, + remote = "https://github.com/povik/yosys-slang.git", +) + +# --- Extensions --- + +llvm = use_extension("@toolchains_llvm//toolchain/extensions:llvm.bzl", "llvm") +llvm.toolchain( + llvm_version = "20.1.8", +) +use_repo(llvm, "llvm_toolchain") + +register_toolchains("@llvm_toolchain//:all") python = use_extension("@rules_python//python/extensions:python.bzl", "python") python.toolchain( @@ -32,15 +82,32 @@ pip.parse( use_repo(pip, "orfs-pip") orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories") - -# To bump version, run: bazelisk run @bazel-orfs//:bump orfs.default( - image = "docker.io/openroad/orfs:v3.0-3273-gedf3d6bf", - # Use local files instead of docker image makefile = "//flow:makefile", makefile_yosys = "//flow:makefile_yosys", pdk = "//flow:asap7", - sha256 = "f5692c6325ebcf27cc348e033355ec95c82c35ace1af7e72a0d352624ada143e", + variables_yaml = "//flow:scripts/variables.yaml", + # Expose the yosys-slang plugin via YOSYS_PLUGIN_PATH so + # SYNTH_HDL_FRONTEND=slang works for ibex, cva6, uart, etc. + yosys_plugins = ["@yosys-slang//src/yosys_plugin:slang.so"], +) +use_repo(orfs, "config") +use_repo(orfs, "gnumake") +use_repo(orfs, "orfs_variable_metadata") + +# Auto-generate orfs_flow() targets from config.mk files. +# See bazel-orfs.md for usage. +orfs_designs = use_repo_rule("@bazel-orfs//private:designs.bzl", "orfs_designs") + +orfs_designs( + name = "orfs_designs", + designs_dir = "//flow/designs:BUILD.bazel", + platforms = [ + "asap7", + "gf180", + "ihp-sg13g2", + "nangate45", + "sky130hd", + "sky130hs", + ], ) -use_repo(orfs, "com_github_nixos_patchelf_download") -use_repo(orfs, "docker_orfs") diff --git a/MODULE.bazel.lock b/MODULE.bazel.lock index ffe386712a..ec414b02c2 100644 --- a/MODULE.bazel.lock +++ b/MODULE.bazel.lock @@ -1,21 +1,46 @@ { - "lockFileVersion": 13, + "lockFileVersion": 24, "registryFileHashes": { "https://bcr.bazel.build/bazel_registry.json": "8a28e4aff06ee60aed2a8c281907fb8bcbf3b753c91fb5a5c57da3215d5b3497", + "https://bcr.bazel.build/modules/abc/0.62-yosyshq/MODULE.bazel": "325231df11fd3480cb0eb3c9095105ccdfacf34583c3a92d8c0ae46967dbaef6", + "https://bcr.bazel.build/modules/abc/0.64-yosyshq.bcr.1/MODULE.bazel": "d1ed5b52014c8b7cf2b8a617f1c1f6e363303c92fd84c6c426281a873d0d297a", + "https://bcr.bazel.build/modules/abc/0.64-yosyshq.bcr.1/source.json": "6c9a69d0cabbe23d1c42d8616405c2e64eabb84e53961872ba2b9ba634c1ffdc", "https://bcr.bazel.build/modules/abseil-cpp/20210324.2/MODULE.bazel": "7cd0312e064fde87c8d1cd79ba06c876bd23630c83466e9500321be55c96ace2", "https://bcr.bazel.build/modules/abseil-cpp/20211102.0/MODULE.bazel": "70390338f7a5106231d20620712f7cccb659cd0e9d073d1991c038eb9fc57589", + "https://bcr.bazel.build/modules/abseil-cpp/20220623.1/MODULE.bazel": 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It lets you build ORFS designs with Bazel +using the same `config.mk` files you already have. + +**Status**: beta -- 59 designs across 6 public PDK platforms have +`orfs_design()` enabled. 53 pass QoR tests; 6 designs are blocked on +upstream fixes (see below). Platforms without public PDK files (gf12, +gf55, rapidus2hp) are not wired up. + +## Quick Start + +```bash +# Install bazelisk (one-time) -- see https://github.com/bazelbuild/bazelisk +# Then, from the ORFS root: + +# Synthesize gcd on asap7 (downloads Docker image on first run) +bazelisk build //flow/designs/asap7/gcd:gcd_synth + +# Run through floorplan +bazelisk build //flow/designs/asap7/gcd:gcd_floorplan + +# Full flow through final +bazelisk build //flow/designs/asap7/gcd:gcd_final + +# Run the test (includes QoR regression check) +bazelisk test //flow/designs/asap7/gcd:gcd_test + +# List all targets for a design +bazelisk query //flow/designs/asap7/gcd:all +``` + +## Available Targets Per Design + +Each enabled design gets these targets automatically from its `config.mk`: + +| Target suffix | What it does | +|---|---| +| `_synth` | Yosys synthesis | +| `_floorplan` | Floorplan + I/O placement | +| `_place` | Global + detailed placement | +| `_cts` | Clock tree synthesis | +| `_grt` | Global routing | +| `_route` | Detailed routing | +| `_final` | Final optimization + fill | +| `_generate_abstract` | LEF/LIB abstract for hierarchical use | +| `_generate_metadata` | Flow metadata (logs, reports) | +| `_test` | Full flow + QoR regression check | + +Each stage depends on the previous one, so building `_final` runs the +entire flow. + +## Working Designs (53 passing tests + 6 blocked) + +All designs below have `orfs_design()` enabled. Designs marked +**(blocked)** fail due to upstream issues in bazel-orfs or the +design's verilog sources. + +### asap7 (18 designs) + +| Design | DESIGN_NAME | Notes | +|--------|-------------|-------| +| `gcd` | gcd | smoketest, ~1 min | +| `gcd-ccs` | gcd | CCS lib model | +| `aes` | aes_cipher_top | medium | +| `aes-block` | aes_cipher_top | block variant | +| `aes-mbff` | aes_cipher_top | MBFF | +| `aes_lvt` | aes_cipher_top | LVT cells | +| `ethmac` | ethmac | Ethernet MAC | +| `ethmac_lvt` | ethmac | LVT cells | +| `ibex` | ibex_core | RISC-V core (slang) | +| `jpeg` | jpeg_encoder | JPEG encoder | +| `jpeg_lvt` | jpeg_encoder | LVT cells | +| `uart` | uart | UART | +| `riscv32i` | riscv_top | RISC-V RV32I | +| `riscv32i-mock-sram` | riscv_top | **(blocked)** PSM-0069 VDD connectivity | +| `mock-cpu` | mock_cpu | mock CPU with FIFO | +| `swerv_wrapper` | swerv_wrapper | SweRV EH1 | +| `cva6` | cva6 | CVA6 RISC-V (~63 min) | +| `mock-alu` | MockAlu | mock ALU | + +### sky130hd (7 designs) + +| Design | DESIGN_NAME | Notes | +|--------|-------------|-------| +| `gcd` | gcd | smoketest | +| `aes` | aes_cipher_top | medium | +| `ibex` | ibex_core | RISC-V core | +| `jpeg` | jpeg_encoder | JPEG encoder | +| `riscv32i` | riscv | RISC-V RV32I | +| `chameleon` | soc_core | SoC with macros | +| `microwatt` | microwatt | POWER ISA core | + +### nangate45 (16 designs) + +| Design | DESIGN_NAME | Notes | +|--------|-------------|-------| +| `gcd` | gcd | smoketest | +| `aes` | aes_cipher_top | medium | +| `ibex` | ibex_core | RISC-V core | +| `jpeg` | jpeg_encoder | JPEG encoder | +| `dynamic_node` | dynamic_node_top_wrap | NoC router | +| `swerv` | swerv | SweRV EH1 | +| `tinyRocket` | RocketTile | RISC-V Rocket | +| `ariane133` | ariane | hierarchical | +| `ariane136` | ariane | hierarchical | +| `black_parrot` | black_parrot | **(blocked)** MPL-0020 macro name mismatch | +| `bp_be_top` | bp_be_top | BP back-end | +| `bp_fe_top` | bp_fe_top | BP front-end | +| `bp_multi_top` | bp_multi_top | **(blocked)** OpenROAD crash in CTS | +| `bp_quad` | black_parrot | **(blocked)** yosys check -assert fails | +| `mempool_group` | mempool_group | **(blocked)** SV macro undefined in synth | +| `swerv_wrapper` | swerv_wrapper | SweRV wrapped | + +### gf180 (6 designs) + +| Design | DESIGN_NAME | Notes | +|--------|-------------|-------| +| `aes` | aes_cipher_top | medium | +| `aes-hybrid` | aes_cipher_top | hybrid variant | +| `ibex` | ibex_core | RISC-V core | +| `jpeg` | jpeg_encoder | JPEG encoder | +| `riscv32i` | riscv | RISC-V RV32I | +| `uart-blocks` | uart | hierarchical with uart_rx block | + +### ihp-sg13g2 (7 designs) + +| Design | DESIGN_NAME | Notes | +|--------|-------------|-------| +| `gcd` | gcd | smoketest | +| `aes` | aes_cipher_top | medium | +| `ibex` | ibex_core | RISC-V core | +| `jpeg` | jpeg_encoder | JPEG encoder | +| `riscv32i` | riscv | RISC-V RV32I | +| `spi` | spi | SPI controller | +| `i2c-gpio-expander` | I2cGpioExpanderTop | **(blocked)** PAD-0102 IO pad instance not found | + +### sky130hs (5 designs) + +| Design | DESIGN_NAME | Notes | +|--------|-------------|-------| +| `gcd` | gcd | smoketest | +| `aes` | aes_cipher_top | medium | +| `ibex` | ibex_core | RISC-V core | +| `jpeg` | jpeg_encoder | JPEG encoder | +| `riscv32i` | riscv | RISC-V RV32I | + +## Designs Not Supported + +### No VERILOG_FILES (minimal) + +`asap7/minimal` is a test design with no `VERILOG_FILES` in config.mk +(empty SDC). Not expected to work with `orfs_designs`. + +### Platforms without public PDK + +gf12, gf55, and rapidus2hp have design directories but no platform +files in the open-source repo. These are skipped entirely. + +## How to Add More Designs + +1. Create `flow/designs///BUILD.bazel`: + +```starlark +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) +``` + +2. If `flow/designs/src//BUILD.bazel` doesn't exist, create it: + +```starlark +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) +``` + +3. Run `bazelisk query //flow/designs//:all` to verify. + +## Using a Local bazel-orfs Checkout + +To iterate on bazel-orfs rules locally, replace the `git_override` in +`MODULE.bazel`: + +```starlark +# Comment out the git_override block, then add: +local_path_override( + module_name = "bazel-orfs", + path = "/path/to/your/bazel-orfs", +) +``` + +Also update the `bazel-orfs-verilog` override: + +```starlark +local_path_override( + module_name = "bazel-orfs-verilog", + path = "/path/to/your/bazel-orfs/verilog", +) +``` + +## Key Differences from Make + +- **Incremental**: Bazel caches every stage. Changing `PLACE_DENSITY` + in `config.mk` rebuilds only floorplan onward -- synthesis is cached. +- **Hermetic**: Tools come from a Docker image (extracted automatically). + No `make install` or `PATH` setup needed. +- **Parallel**: Independent designs build in parallel automatically. +- **Reproducible**: Same inputs always produce the same outputs. + +## Performance Notes + +Each OpenROAD invocation uses `-threads ` (all available cores). +When Bazel runs many designs in parallel, the machine becomes heavily +overcommitted. On a 48-core machine, 50+ OpenROAD instances may run +simultaneously during a full `bazelisk test ...`, each requesting 48 +threads. + +To limit parallelism: + +```bash +# Limit to 4 concurrent OpenROAD invocations +bazelisk test --jobs=4 ... +``` + +A full test suite run (53 designs, 6 platforms) takes roughly 4-5 hours +on a 48-core machine with default parallelism (overcommitted). Individual +design times vary from ~1 minute (gcd) to ~63 minutes (cva6 on asap7). + +## Updating Metric Thresholds + +When OpenROAD or flow scripts change, metric thresholds in +`rules-base.json` may go stale. To update them for a specific design: + +```bash +# Rebuilds the design and writes updated thresholds back to source +bazelisk run //flow/designs/asap7/aes-block:aes_cipher_top_update +``` + +The target name follows the pattern `_update` where +`` comes from `DESIGN_NAME` in `config.mk`. + +## Equivalence Checking (eqy) + +Some designs (e.g. `aes`) set `EQUIVALENCE_CHECK=1` in their +`config.mk` to enable equivalence checking of repair_timing. The +actual `eqy` tool invocation is gated by a separate `RUN_EQY` +variable (default 0), so builds don't fail when eqy is not installed. +CI sets `RUN_EQY=1` when eqy is available. + +## Workflow: Unmerged Commits + +This PR serves as a working branch against master. Commits here are +spun off as separate, focused PRs for review. Once a PR merges, this +branch is rebased on master to drop the merged commit. The branch is +force-pushed after each rebase so the PR commit list is always the +source of truth for what's pending. + +Filing of PRs is throttled to avoid overwhelming maintainers -- +submitting too many at once just causes "maintainer packet dropping" +where reviews stall. + +## Known Limitations + +- The Docker image is pinned; updating it requires changing + `MODULE.bazel`. +- Platforms without public PDK files (gf12, gf55, rapidus2hp) are not + supported. +- **black_parrot**: macro_placement.tcl references macro names that + don't match the synthesized netlist (MPL-0020). +- **bp_multi_top**: OpenROAD crashes (SIGSEGV) during CTS timing + analysis. +- **bp_quad**: yosys `check -assert` finds 9 problems during synthesis. +- **i2c-gpio-expander**: IO pad instance `sg13g2_IOPad_io_gpio_3` not + found during floorplan (PAD-0102). +- **mempool_group**: SystemVerilog macros (`AXI_TYPEDEF_RESP_T` etc.) + are undefined -- likely a missing include path in the bazel build. +- **riscv32i-mock-sram**: VDD connectivity check fails at final stage + (PSM-0069) -- fakeram macro power pins are unconnected. +- This is a beta -- expect rough edges. File issues at + https://github.com/The-OpenROAD-Project/bazel-orfs/issues diff --git a/flow/BUILD.bazel b/flow/BUILD.bazel index 62e0125948..9f6c5b5476 100644 --- a/flow/BUILD.bazel +++ b/flow/BUILD.bazel @@ -1,7 +1,9 @@ load("@bazel-orfs//:openroad.bzl", "orfs_pdk") +# Export platform files so designs can reference them directly via +# ADDITIONAL_LEFS, ADDITIONAL_LIBS, etc. from PLATFORM_DIR. exports_files( - ["scripts/variables.yaml"], + ["scripts/variables.yaml"] + glob(["platforms/**"]), visibility = ["//visibility:public"], ) @@ -20,6 +22,7 @@ filegroup( srcs = ["Makefile"], data = glob(MAKEFILE_SHARED + [ "scripts/*.script", + "scripts/*.v", "scripts/util.tcl", "scripts/synth*.tcl", "scripts/synth*.v", @@ -50,23 +53,14 @@ filegroup( ext = ext, pdk = pdk, ) - for ext in [ - "gds", - "lef", - "lyp", - "lyt", - "mk", - "rules", - "tcl", - "v", - ] + { - "asap7": ["cfg", "json", "lib.gz", "sdc"], - "gf180": ["cfg", "layermap", "lyt_generic"], - "ihp-sg13g2": ["json"], - "nangate45": ["cfg"], - "sky130hd": ["json", "tlef"], - "sky130hs": ["json", "tlef"], - }.get(pdk, []) + for ext in { + "asap7": ["cfg", "gds", "lef", "lib", "lib.gz", "lyt", "mk", "rules", "sdc", "sv", "tcl", "v"], + "gf180": ["cfg", "gds", "lef", "lib.gz", "lyt", "mk", "rules", "tcl", "v"], + "ihp-sg13g2": ["gds", "json", "lef", "lib", "lyt", "mk", "rules", "tcl", "v"], + "nangate45": ["cfg", "gds", "lef", "lib", "lyt", "mk", "rules", "tcl", "v"], + "sky130hd": ["gds", "lef", "lib", "lyt", "mk", "rules", "tcl", "tlef", "v"], + "sky130hs": ["gds", "lef", "lib", "lyt", "mk", "rules", "tcl", "tlef", "v"], + }[pdk] ] + [ "platforms/common/**/*.v", ]), diff --git a/flow/designs/BUILD.bazel b/flow/designs/BUILD.bazel new file mode 100644 index 0000000000..ed4e50dd79 --- /dev/null +++ b/flow/designs/BUILD.bazel @@ -0,0 +1 @@ +exports_files(["BUILD.bazel"]) diff --git a/flow/designs/asap7/aes-block/BUILD.bazel b/flow/designs/asap7/aes-block/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/asap7/aes-block/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/asap7/aes-mbff/BUILD.bazel b/flow/designs/asap7/aes-mbff/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/asap7/aes-mbff/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/asap7/aes/BUILD.bazel b/flow/designs/asap7/aes/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/asap7/aes/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/asap7/aes_lvt/BUILD.bazel b/flow/designs/asap7/aes_lvt/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/asap7/aes_lvt/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/asap7/cva6/BUILD.bazel b/flow/designs/asap7/cva6/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/asap7/cva6/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/asap7/ethmac/BUILD.bazel b/flow/designs/asap7/ethmac/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/asap7/ethmac/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/asap7/ethmac_lvt/BUILD.bazel b/flow/designs/asap7/ethmac_lvt/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/asap7/ethmac_lvt/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/asap7/gcd-ccs/BUILD.bazel b/flow/designs/asap7/gcd-ccs/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/asap7/gcd-ccs/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/asap7/gcd/BUILD.bazel b/flow/designs/asap7/gcd/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/asap7/gcd/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/asap7/ibex/BUILD.bazel b/flow/designs/asap7/ibex/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/asap7/ibex/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/asap7/jpeg/BUILD.bazel b/flow/designs/asap7/jpeg/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/asap7/jpeg/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/asap7/jpeg_lvt/BUILD.bazel b/flow/designs/asap7/jpeg_lvt/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/asap7/jpeg_lvt/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/asap7/minimal/BUILD.bazel b/flow/designs/asap7/minimal/BUILD.bazel new file mode 100644 index 0000000000..3835f0fd1c --- /dev/null +++ b/flow/designs/asap7/minimal/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +# TODO(bazel-orfs): orfs_design(designs = DESIGNS) +# Blocked: no VERILOG_FILES in config.mk (test-only design with empty SDC). diff --git a/flow/designs/asap7/mock-alu/BUILD.bazel b/flow/designs/asap7/mock-alu/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/asap7/mock-alu/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/asap7/mock-cpu/BUILD.bazel b/flow/designs/asap7/mock-cpu/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/asap7/mock-cpu/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/asap7/riscv32i-mock-sram/BUILD.bazel b/flow/designs/asap7/riscv32i-mock-sram/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/asap7/riscv32i-mock-sram/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/asap7/riscv32i/BUILD.bazel b/flow/designs/asap7/riscv32i/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/asap7/riscv32i/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/asap7/swerv_wrapper/BUILD.bazel b/flow/designs/asap7/swerv_wrapper/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/asap7/swerv_wrapper/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/asap7/swerv_wrapper/lef/BUILD.bazel b/flow/designs/asap7/swerv_wrapper/lef/BUILD.bazel new file mode 100644 index 0000000000..4419ddd7a3 --- /dev/null +++ b/flow/designs/asap7/swerv_wrapper/lef/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.lef"]), + visibility = ["//visibility:public"], +) + +filegroup( + name = "lef", + srcs = glob(["*.lef"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/asap7/swerv_wrapper/lib/BUILD.bazel b/flow/designs/asap7/swerv_wrapper/lib/BUILD.bazel new file mode 100644 index 0000000000..5a1c76dc01 --- /dev/null +++ b/flow/designs/asap7/swerv_wrapper/lib/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.lib"]), + visibility = ["//visibility:public"], +) + +filegroup( + name = "lib", + srcs = glob(["*.lib"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/asap7/uart/BUILD.bazel b/flow/designs/asap7/uart/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/asap7/uart/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/gf180/aes-hybrid/BUILD.bazel b/flow/designs/gf180/aes-hybrid/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/gf180/aes-hybrid/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/gf180/aes-hybrid/rules-base.json b/flow/designs/gf180/aes-hybrid/rules-base.json index 42ece06169..b84e9c6447 100644 --- a/flow/designs/gf180/aes-hybrid/rules-base.json +++ b/flow/designs/gf180/aes-hybrid/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 489779.41376, + "value": 634000.0, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 650139, + "value": 834351, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 21903, + "value": 24157, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1831, + "value": 2101, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1831, + "value": 2101, "compare": "<=" }, "cts__timing__setup__ws": { - "value": -1.14, + "value": -1.02, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -137.0, + "value": -113.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -154.0, + "value": -143.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 1501193, + "value": 1869441, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -80,11 +80,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.28, + "value": -1.26, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -148.0, + "value": -140.0, "compare": ">=" }, "finish__timing__hold__ws": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 752796, + "value": 895937, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/gf180/aes/BUILD.bazel b/flow/designs/gf180/aes/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/gf180/aes/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/gf180/ibex/BUILD.bazel b/flow/designs/gf180/ibex/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/gf180/ibex/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/gf180/jpeg/BUILD.bazel b/flow/designs/gf180/jpeg/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/gf180/jpeg/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/gf180/riscv32i/BUILD.bazel b/flow/designs/gf180/riscv32i/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/gf180/riscv32i/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/gf180/uart-blocks/BUILD.bazel b/flow/designs/gf180/uart-blocks/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/gf180/uart-blocks/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/gf180/uart-blocks/rules-base.json b/flow/designs/gf180/uart-blocks/rules-base.json index de20a48fd8..770b2e415a 100644 --- a/flow/designs/gf180/uart-blocks/rules-base.json +++ b/flow/designs/gf180/uart-blocks/rules-base.json @@ -1,18 +1,14 @@ { - "synth__design__instance__area__stdcell": { - "value": 61300.0, - "compare": "<=" - }, "constraints__clocks__count": { - "value": 1, + "value": 0, "compare": "==" }, "placeopt__design__instance__area": { - "value": 69126, + "value": 70862, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 714, + "value": 743, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,27 +16,27 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 62, + "value": 65, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 62, + "value": 65, "compare": "<=" }, "cts__timing__setup__ws": { - "value": -0.3, + "value": 0.0, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -1.2, + "value": 0.0, "compare": ">=" }, "cts__timing__hold__ws": { - "value": -0.3, + "value": 0.0, "compare": ">=" }, "cts__timing__hold__tns": { - "value": -1.2, + "value": 0.0, "compare": ">=" }, "globalroute__antenna_diodes_count": { @@ -48,23 +44,23 @@ "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -0.3, + "value": 0.0, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -1.2, + "value": 0.0, "compare": ">=" }, "globalroute__timing__hold__ws": { - "value": -0.3, + "value": 0.0, "compare": ">=" }, "globalroute__timing__hold__tns": { - "value": -1.2, + "value": 0.0, "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 21354, + "value": 19283, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -80,23 +76,23 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.3, + "value": 0.0, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -1.2, + "value": 0.0, "compare": ">=" }, "finish__timing__hold__ws": { - "value": -0.3, + "value": 0.0, "compare": ">=" }, "finish__timing__hold__tns": { - "value": -1.2, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 70132, + "value": 70862, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel b/flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/ihp-sg13g2/aes/BUILD.bazel b/flow/designs/ihp-sg13g2/aes/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/ihp-sg13g2/aes/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/ihp-sg13g2/gcd/BUILD.bazel b/flow/designs/ihp-sg13g2/gcd/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/ihp-sg13g2/gcd/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel b/flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/ihp-sg13g2/ibex/BUILD.bazel b/flow/designs/ihp-sg13g2/ibex/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/ihp-sg13g2/ibex/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/ihp-sg13g2/jpeg/BUILD.bazel b/flow/designs/ihp-sg13g2/jpeg/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/ihp-sg13g2/jpeg/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel b/flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/ihp-sg13g2/spi/BUILD.bazel b/flow/designs/ihp-sg13g2/spi/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/ihp-sg13g2/spi/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/nangate45/aes/BUILD.bazel b/flow/designs/nangate45/aes/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/nangate45/aes/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/nangate45/ariane133/BUILD.bazel b/flow/designs/nangate45/ariane133/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/nangate45/ariane133/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/nangate45/ariane136/BUILD.bazel b/flow/designs/nangate45/ariane136/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/nangate45/ariane136/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/nangate45/ariane136/rules-base.json b/flow/designs/nangate45/ariane136/rules-base.json index e48b97d4ae..5657ee419c 100644 --- a/flow/designs/nangate45/ariane136/rules-base.json +++ b/flow/designs/nangate45/ariane136/rules-base.json @@ -1,18 +1,14 @@ { - "synth__design__instance__area__stdcell": { - "value": 845000.0, - "compare": "<=" - }, "constraints__clocks__count": { - "value": 1, + "value": 0, "compare": "==" }, "placeopt__design__instance__area": { - "value": 847520, + "value": 853835, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 196993, + "value": 208889, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,51 +16,51 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 17130, + "value": 18164, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 17130, + "value": 18164, "compare": "<=" }, "cts__timing__setup__ws": { - "value": -0.3, + "value": 0.0, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -1.2, + "value": 0.0, "compare": ">=" }, "cts__timing__hold__ws": { - "value": -0.678, + "value": 0.0, "compare": ">=" }, "cts__timing__hold__tns": { - "value": -8.05, + "value": 0.0, "compare": ">=" }, "globalroute__antenna_diodes_count": { - "value": 200, + "value": 196, "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -0.3, + "value": 0.0, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -1.2, + "value": 0.0, "compare": ">=" }, "globalroute__timing__hold__ws": { - "value": -0.3, + "value": 0.0, "compare": ">=" }, "globalroute__timing__hold__tns": { - "value": -1.2, + "value": 0.0, "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 8033923, + "value": 7740320, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -76,27 +72,27 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 201, + "value": 196, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.3, + "value": 0.0, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -1.2, + "value": 0.0, "compare": ">=" }, "finish__timing__hold__ws": { - "value": -0.3, + "value": 0.0, "compare": ">=" }, "finish__timing__hold__tns": { - "value": -1.2, + "value": 0.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 858672, + "value": 853954, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/black_parrot/BUILD.bazel b/flow/designs/nangate45/black_parrot/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/nangate45/black_parrot/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/nangate45/bp_be_top/BUILD.bazel b/flow/designs/nangate45/bp_be_top/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/nangate45/bp_be_top/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/nangate45/bp_be_top/rules-base.json b/flow/designs/nangate45/bp_be_top/rules-base.json index 2140525de9..876f707c29 100644 --- a/flow/designs/nangate45/bp_be_top/rules-base.json +++ b/flow/designs/nangate45/bp_be_top/rules-base.json @@ -1,18 +1,14 @@ { - "synth__design__instance__area__stdcell": { - "value": 268204.56, - "compare": "<=" - }, "constraints__clocks__count": { - "value": 1, + "value": 0, "compare": "==" }, "placeopt__design__instance__area": { - "value": 273548, + "value": 310391, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 62588, + "value": 84218, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +16,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 5442, + "value": 7323, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 5442, + "value": 7323, "compare": "<=" }, "cts__timing__setup__ws": { - "value": -0.411, + "value": 0.0, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -24.3, + "value": 0.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -44,15 +40,15 @@ "compare": ">=" }, "globalroute__antenna_diodes_count": { - "value": 0, + "value": 100, "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -0.427, + "value": 0.0, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -29.9, + "value": 0.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -64,7 +60,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 2504235, + "value": 2732383, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -76,15 +72,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 5, + "value": 100, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.418, + "value": 0.0, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -28.5, + "value": 0.0, "compare": ">=" }, "finish__timing__hold__ws": { @@ -96,7 +92,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 275387, + "value": 310405, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/bp_fe_top/BUILD.bazel b/flow/designs/nangate45/bp_fe_top/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/nangate45/bp_fe_top/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/nangate45/bp_multi_top/BUILD.bazel b/flow/designs/nangate45/bp_multi_top/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/nangate45/bp_multi_top/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/nangate45/bp_quad/BUILD.bazel b/flow/designs/nangate45/bp_quad/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/nangate45/bp_quad/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/nangate45/dynamic_node/BUILD.bazel b/flow/designs/nangate45/dynamic_node/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/nangate45/dynamic_node/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/nangate45/gcd/BUILD.bazel b/flow/designs/nangate45/gcd/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/nangate45/gcd/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/nangate45/ibex/BUILD.bazel b/flow/designs/nangate45/ibex/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/nangate45/ibex/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/nangate45/jpeg/BUILD.bazel b/flow/designs/nangate45/jpeg/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/nangate45/jpeg/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/nangate45/mempool_group/BUILD.bazel b/flow/designs/nangate45/mempool_group/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/nangate45/mempool_group/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/nangate45/swerv/BUILD.bazel b/flow/designs/nangate45/swerv/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/nangate45/swerv/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/nangate45/swerv_wrapper/BUILD.bazel b/flow/designs/nangate45/swerv_wrapper/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/nangate45/swerv_wrapper/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/nangate45/tinyRocket/BUILD.bazel b/flow/designs/nangate45/tinyRocket/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/nangate45/tinyRocket/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/sky130hd/aes/BUILD.bazel b/flow/designs/sky130hd/aes/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/sky130hd/aes/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/sky130hd/chameleon/BUILD.bazel b/flow/designs/sky130hd/chameleon/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/sky130hd/chameleon/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/sky130hd/chameleon/gds/BUILD.bazel b/flow/designs/sky130hd/chameleon/gds/BUILD.bazel new file mode 100644 index 0000000000..64d9152242 --- /dev/null +++ b/flow/designs/sky130hd/chameleon/gds/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.gds", "*.gds.gz"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "gds", + srcs = glob(["*.gds", "*.gds.gz"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/sky130hd/chameleon/lef/BUILD.bazel b/flow/designs/sky130hd/chameleon/lef/BUILD.bazel new file mode 100644 index 0000000000..4419ddd7a3 --- /dev/null +++ b/flow/designs/sky130hd/chameleon/lef/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.lef"]), + visibility = ["//visibility:public"], +) + +filegroup( + name = "lef", + srcs = glob(["*.lef"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/sky130hd/gcd/BUILD.bazel b/flow/designs/sky130hd/gcd/BUILD.bazel new file mode 100644 index 0000000000..1054ff782a --- /dev/null +++ b/flow/designs/sky130hd/gcd/BUILD.bazel @@ -0,0 +1,6 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) diff --git a/flow/designs/sky130hd/ibex/BUILD.bazel b/flow/designs/sky130hd/ibex/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/sky130hd/ibex/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/sky130hd/jpeg/BUILD.bazel b/flow/designs/sky130hd/jpeg/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/sky130hd/jpeg/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/sky130hd/microwatt/BUILD.bazel b/flow/designs/sky130hd/microwatt/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/sky130hd/microwatt/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/sky130hd/microwatt/gds/BUILD.bazel b/flow/designs/sky130hd/microwatt/gds/BUILD.bazel new file mode 100644 index 0000000000..64d9152242 --- /dev/null +++ b/flow/designs/sky130hd/microwatt/gds/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.gds", "*.gds.gz"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "gds", + srcs = glob(["*.gds", "*.gds.gz"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/sky130hd/microwatt/lef/BUILD.bazel b/flow/designs/sky130hd/microwatt/lef/BUILD.bazel new file mode 100644 index 0000000000..4419ddd7a3 --- /dev/null +++ b/flow/designs/sky130hd/microwatt/lef/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.lef"]), + visibility = ["//visibility:public"], +) + +filegroup( + name = "lef", + srcs = glob(["*.lef"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/sky130hd/microwatt/lib/BUILD.bazel b/flow/designs/sky130hd/microwatt/lib/BUILD.bazel new file mode 100644 index 0000000000..5a1c76dc01 --- /dev/null +++ b/flow/designs/sky130hd/microwatt/lib/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.lib"]), + visibility = ["//visibility:public"], +) + +filegroup( + name = "lib", + srcs = glob(["*.lib"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/sky130hd/riscv32i/BUILD.bazel b/flow/designs/sky130hd/riscv32i/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/sky130hd/riscv32i/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/sky130hs/aes/BUILD.bazel b/flow/designs/sky130hs/aes/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/sky130hs/aes/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/sky130hs/gcd/BUILD.bazel b/flow/designs/sky130hs/gcd/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/sky130hs/gcd/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/sky130hs/ibex/BUILD.bazel b/flow/designs/sky130hs/ibex/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/sky130hs/ibex/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/sky130hs/jpeg/BUILD.bazel b/flow/designs/sky130hs/jpeg/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/sky130hs/jpeg/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/sky130hs/riscv32i/BUILD.bazel b/flow/designs/sky130hs/riscv32i/BUILD.bazel new file mode 100644 index 0000000000..9ddf31b8b6 --- /dev/null +++ b/flow/designs/sky130hs/riscv32i/BUILD.bazel @@ -0,0 +1,7 @@ +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +exports_files(glob(["*"])) + +orfs_design(designs = DESIGNS) + diff --git a/flow/designs/src/aes/BUILD.bazel b/flow/designs/src/aes/BUILD.bazel new file mode 100644 index 0000000000..3a5e9ed8a7 --- /dev/null +++ b/flow/designs/src/aes/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/ariane/BUILD.bazel b/flow/designs/src/ariane/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/ariane/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/ariane133/BUILD.bazel b/flow/designs/src/ariane133/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/ariane133/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/ariane136/BUILD.bazel b/flow/designs/src/ariane136/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/ariane136/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/black_parrot/BUILD.bazel b/flow/designs/src/black_parrot/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/black_parrot/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/bp_be_top/BUILD.bazel b/flow/designs/src/bp_be_top/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/bp_be_top/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/bp_fe_top/BUILD.bazel b/flow/designs/src/bp_fe_top/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/bp_fe_top/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/bp_multi_top/BUILD.bazel b/flow/designs/src/bp_multi_top/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/bp_multi_top/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/bp_quad/BUILD.bazel b/flow/designs/src/bp_quad/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/bp_quad/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/chameleon/AHB_sys_0/APB_sys_0/BUILD.bazel b/flow/designs/src/chameleon/AHB_sys_0/APB_sys_0/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/chameleon/AHB_sys_0/APB_sys_0/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/chameleon/AHB_sys_0/BUILD.bazel b/flow/designs/src/chameleon/AHB_sys_0/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/chameleon/AHB_sys_0/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/chameleon/BUILD.bazel b/flow/designs/src/chameleon/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/chameleon/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/chameleon/IPs/BUILD.bazel b/flow/designs/src/chameleon/IPs/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/chameleon/IPs/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/chameleon/IPs/apb2i2c/BUILD.bazel b/flow/designs/src/chameleon/IPs/apb2i2c/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/chameleon/IPs/apb2i2c/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/chameleon/acc/BUILD.bazel b/flow/designs/src/chameleon/acc/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/chameleon/acc/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/chameleon/ibex/BUILD.bazel b/flow/designs/src/chameleon/ibex/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/chameleon/ibex/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/chameleon/ibex/models/BUILD.bazel b/flow/designs/src/chameleon/ibex/models/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/chameleon/ibex/models/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/coyote/BUILD.bazel b/flow/designs/src/coyote/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/coyote/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/BUILD.bazel b/flow/designs/src/cva6/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/common/BUILD.bazel b/flow/designs/src/cva6/common/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/common/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/common/local/BUILD.bazel b/flow/designs/src/cva6/common/local/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/common/local/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/common/local/util/BUILD.bazel b/flow/designs/src/cva6/common/local/util/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/common/local/util/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/BUILD.bazel b/flow/designs/src/cva6/core/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cache_subsystem/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/BUILD.bazel new file mode 100644 index 0000000000..f31c831d67 --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/BUILD.bazel @@ -0,0 +1,16 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "include", + srcs = glob(include = ["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cva6_mmu/BUILD.bazel b/flow/designs/src/cva6/core/cva6_mmu/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cva6_mmu/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cvfpu/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cvfpu/src/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cvfpu/src/common_cells/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/common_cells/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/common_cells/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cvfpu/src/common_cells/include/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/common_cells/include/BUILD.bazel new file mode 100644 index 0000000000..5ac3e69416 --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/common_cells/include/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["**/*.v", "**/*.sv", "**/*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "include", + srcs = glob(include = ["**/*.v", "**/*.sv", "**/*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cvxif_example/BUILD.bazel b/flow/designs/src/cva6/core/cvxif_example/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cvxif_example/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/cvxif_example/include/BUILD.bazel b/flow/designs/src/cva6/core/cvxif_example/include/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/cvxif_example/include/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/frontend/BUILD.bazel b/flow/designs/src/cva6/core/frontend/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/frontend/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/include/BUILD.bazel b/flow/designs/src/cva6/core/include/BUILD.bazel new file mode 100644 index 0000000000..f31c831d67 --- /dev/null +++ b/flow/designs/src/cva6/core/include/BUILD.bazel @@ -0,0 +1,16 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "include", + srcs = glob(include = ["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/pmp/BUILD.bazel b/flow/designs/src/cva6/core/pmp/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/pmp/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/core/pmp/src/BUILD.bazel b/flow/designs/src/cva6/core/pmp/src/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/core/pmp/src/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/vendor/BUILD.bazel b/flow/designs/src/cva6/vendor/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/vendor/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/vendor/pulp-platform/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/vendor/pulp-platform/axi/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/axi/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/axi/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/vendor/pulp-platform/axi/src/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/axi/src/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/axi/src/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/BUILD.bazel new file mode 100644 index 0000000000..7799a07b4f --- /dev/null +++ b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/dynamic_node/BUILD.bazel b/flow/designs/src/dynamic_node/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/dynamic_node/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/ethmac/BUILD.bazel b/flow/designs/src/ethmac/BUILD.bazel new file mode 100644 index 0000000000..3a5e9ed8a7 --- /dev/null +++ b/flow/designs/src/ethmac/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/fifo/BUILD.bazel b/flow/designs/src/fifo/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/fifo/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/gcd/BUILD.bazel b/flow/designs/src/gcd/BUILD.bazel new file mode 100644 index 0000000000..3a5e9ed8a7 --- /dev/null +++ b/flow/designs/src/gcd/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/ibex_sv/BUILD.bazel b/flow/designs/src/ibex_sv/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/ibex_sv/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/ibex_sv/syn/BUILD.bazel b/flow/designs/src/ibex_sv/syn/BUILD.bazel new file mode 100644 index 0000000000..4b9b07d8a7 --- /dev/null +++ b/flow/designs/src/ibex_sv/syn/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/ibex_sv/syn/rtl/BUILD.bazel b/flow/designs/src/ibex_sv/syn/rtl/BUILD.bazel new file mode 100644 index 0000000000..4b9b07d8a7 --- /dev/null +++ b/flow/designs/src/ibex_sv/syn/rtl/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/ibex_sv/vendor/BUILD.bazel b/flow/designs/src/ibex_sv/vendor/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/ibex_sv/vendor/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/BUILD.bazel b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/BUILD.bazel b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/BUILD.bazel b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/BUILD.bazel new file mode 100644 index 0000000000..614a16235f --- /dev/null +++ b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "include", + srcs = glob(include = ["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/jpeg/BUILD.bazel b/flow/designs/src/jpeg/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/jpeg/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/jpeg/include/BUILD.bazel b/flow/designs/src/jpeg/include/BUILD.bazel new file mode 100644 index 0000000000..2f7e49e5f9 --- /dev/null +++ b/flow/designs/src/jpeg/include/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "include", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/BUILD.bazel b/flow/designs/src/mempool_group/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/mempool_group/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/BUILD.bazel b/flow/designs/src/mempool_group/rtl/BUILD.bazel new file mode 100644 index 0000000000..4839ec86b0 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/BUILD.bazel @@ -0,0 +1,16 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "include", + srcs = glob(["*.v", "*.sv", "*.svh"], allow_empty = True) + [ + "//flow/designs/src/mempool_group/rtl/axi:assign.svh", + "//flow/designs/src/mempool_group/rtl/axi:typedef.svh", + "//flow/designs/src/mempool_group/rtl/common_cells:assertions.svh", + "//flow/designs/src/mempool_group/rtl/common_cells:registers.svh", + "//flow/designs/src/mempool_group/rtl/mempool:mempool.svh", + ], + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/axi/BUILD.bazel b/flow/designs/src/mempool_group/rtl/axi/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/axi/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/axi/src/BUILD.bazel b/flow/designs/src/mempool_group/rtl/axi/src/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/axi/src/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/BUILD.bazel b/flow/designs/src/mempool_group/rtl/cluster_interconnect/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/cluster_interconnect/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/BUILD.bazel b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/BUILD.bazel b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/BUILD.bazel b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/common_cells/BUILD.bazel b/flow/designs/src/mempool_group/rtl/common_cells/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/BUILD.bazel b/flow/designs/src/mempool_group/rtl/common_cells/src/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/BUILD.bazel b/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/mempool/BUILD.bazel b/flow/designs/src/mempool_group/rtl/mempool/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/mempool/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/register_interface/BUILD.bazel b/flow/designs/src/mempool_group/rtl/register_interface/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/register_interface/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/register_interface/include/BUILD.bazel b/flow/designs/src/mempool_group/rtl/register_interface/include/BUILD.bazel new file mode 100644 index 0000000000..0127fa1306 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/register_interface/include/BUILD.bazel @@ -0,0 +1,13 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "include", + srcs = glob(["*.v", "*.sv", "*.svh"], allow_empty = True) + [ + "//flow/designs/src/mempool_group/rtl/register_interface/include/register_interface:assign.svh", + "//flow/designs/src/mempool_group/rtl/register_interface/include/register_interface:typedef.svh", + ], + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/BUILD.bazel b/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/snitch/BUILD.bazel b/flow/designs/src/mempool_group/rtl/snitch/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/BUILD.bazel b/flow/designs/src/mempool_group/rtl/snitch/src/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/BUILD.bazel b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/tech_cells_generic/BUILD.bazel b/flow/designs/src/mempool_group/rtl/tech_cells_generic/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/tech_cells_generic/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/BUILD.bazel b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/BUILD.bazel b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/BUILD.bazel new file mode 100644 index 0000000000..cf79c553b7 --- /dev/null +++ b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*.v", "*.sv", "*.svh"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/microwatt/BUILD.bazel b/flow/designs/src/microwatt/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/microwatt/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/microwatt/IPs/BUILD.bazel b/flow/designs/src/microwatt/IPs/BUILD.bazel new file mode 100644 index 0000000000..de61a2428b --- /dev/null +++ b/flow/designs/src/microwatt/IPs/BUILD.bazel @@ -0,0 +1,16 @@ +exports_files( + glob(["*"]), + visibility = ["//visibility:public"], +) + +filegroup( + name = "IPs", + srcs = glob(["*"]), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mock-alu/BUILD.bazel b/flow/designs/src/mock-alu/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/mock-alu/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/mock-array/BUILD.bazel b/flow/designs/src/mock-array/BUILD.bazel new file mode 100644 index 0000000000..50d9202992 --- /dev/null +++ b/flow/designs/src/mock-array/BUILD.bazel @@ -0,0 +1,4 @@ +exports_files( + glob(["*"]), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/riscv32i/BUILD.bazel b/flow/designs/src/riscv32i/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/riscv32i/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/spi/BUILD.bazel b/flow/designs/src/spi/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/spi/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/swerv/BUILD.bazel b/flow/designs/src/swerv/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/swerv/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/tinyRocket/BUILD.bazel b/flow/designs/src/tinyRocket/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/tinyRocket/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/uart-no-param/BUILD.bazel b/flow/designs/src/uart-no-param/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/uart-no-param/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/src/uart/BUILD.bazel b/flow/designs/src/uart/BUILD.bazel new file mode 100644 index 0000000000..8ccd944700 --- /dev/null +++ b/flow/designs/src/uart/BUILD.bazel @@ -0,0 +1,10 @@ +exports_files( + glob(["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) + +filegroup( + name = "verilog", + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index c8cbfb7898..4f646c3299 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -1585,3 +1585,55 @@ CDL_FILE: for generating Circuit Description Language output. stages: - final +LIB_MODEL: + description: > + Selects the standard cell library timing model. Set to CCS to use + composite current source liberty files; default selects the NLDM + (non-linear delay model) variant. + stages: + - synth + - floorplan + - place + - cts + - grt + - route + - final +MIN_CLK_ROUTING_LAYER: + description: > + Lowest metal layer that clock tree synthesis may use for clock + routing. Mirrors MIN_ROUTING_LAYER but applies to clock nets. + stages: + - cts +SDC_FILE_EXTRA: + description: > + Path to an additional Tcl file sourced from constraint.sdc and from + place_pins I/O scripts. Used by designs that share helper Tcl + between SDC and pin placement (e.g. mock-cpu). + stages: + - synth + - floorplan + - place + - cts + - grt + - route + - final +SYNTH_NUM_PARTITIONS: + description: > + Total number of partitions used by the parallel synthesis flow. + Set automatically by bazel-orfs based on SYNTH_KEEP_MODULES; not + typically set by users. + stages: + - synth +MOCK_ALU_OPERATIONS: + description: > + Comma-separated list of ALU operations baked into the generated + mock-alu RTL (e.g. ADD,SUB,AND). Consumed by the Chisel generator + in src/mock-alu. + stages: + - synth +MOCK_ALU_WIDTH: + description: > + Datapath width in bits for the generated mock-alu RTL. Consumed by + the Chisel generator in src/mock-alu. + stages: + - synth From ec47e43b7bc60bad46b9d48ff0fbd7466103639d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 21:28:09 +0200 Subject: [PATCH 02/28] fix: address Gemini review feedback on PR #4208 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - flow/BUILD.bazel: use .get(pdk, []) instead of [pdk] for the per-PDK extension dict so adding a PDK to the iteration list without a matching dict entry no longer crashes with KeyError. - flow/designs/gf180/uart-blocks/rules-base.json: revert to master's version. The branch's regenerated copy had constraints__clocks__count dropped to 0 (timing constraints not applied) and was missing synth__design__instance__area__stdcell. - flow/designs/src/{aes,ethmac,gcd}/BUILD.bazel: include *.sv in the verilog filegroup glob so it matches exports_files and the rest of the design BUILD files (allow_empty since none currently exist). Signed-off-by: Øyvind Harboe --- flow/BUILD.bazel | 2 +- .../designs/gf180/uart-blocks/rules-base.json | 42 ++++++++++--------- flow/designs/src/aes/BUILD.bazel | 2 +- flow/designs/src/ethmac/BUILD.bazel | 2 +- flow/designs/src/gcd/BUILD.bazel | 2 +- 5 files changed, 27 insertions(+), 23 deletions(-) diff --git a/flow/BUILD.bazel b/flow/BUILD.bazel index 9f6c5b5476..b6d4efc49f 100644 --- a/flow/BUILD.bazel +++ b/flow/BUILD.bazel @@ -60,7 +60,7 @@ filegroup( "nangate45": ["cfg", "gds", "lef", "lib", "lyt", "mk", "rules", "tcl", "v"], "sky130hd": ["gds", "lef", "lib", "lyt", "mk", "rules", "tcl", "tlef", "v"], "sky130hs": ["gds", "lef", "lib", "lyt", "mk", "rules", "tcl", "tlef", "v"], - }[pdk] + }.get(pdk, []) ] + [ "platforms/common/**/*.v", ]), diff --git a/flow/designs/gf180/uart-blocks/rules-base.json b/flow/designs/gf180/uart-blocks/rules-base.json index 770b2e415a..de20a48fd8 100644 --- a/flow/designs/gf180/uart-blocks/rules-base.json +++ b/flow/designs/gf180/uart-blocks/rules-base.json @@ -1,14 +1,18 @@ { + "synth__design__instance__area__stdcell": { + "value": 61300.0, + "compare": "<=" + }, "constraints__clocks__count": { - "value": 0, + "value": 1, "compare": "==" }, "placeopt__design__instance__area": { - "value": 70862, + "value": 69126, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 743, + "value": 714, "compare": "<=" }, "detailedplace__design__violations": { @@ -16,27 +20,27 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 65, + "value": 62, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 65, + "value": 62, "compare": "<=" }, "cts__timing__setup__ws": { - "value": 0.0, + "value": -0.3, "compare": ">=" }, "cts__timing__setup__tns": { - "value": 0.0, + "value": -1.2, "compare": ">=" }, "cts__timing__hold__ws": { - "value": 0.0, + "value": -0.3, "compare": ">=" }, "cts__timing__hold__tns": { - "value": 0.0, + "value": -1.2, "compare": ">=" }, "globalroute__antenna_diodes_count": { @@ -44,23 +48,23 @@ "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": 0.0, + "value": -0.3, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": 0.0, + "value": -1.2, "compare": ">=" }, "globalroute__timing__hold__ws": { - "value": 0.0, + "value": -0.3, "compare": ">=" }, "globalroute__timing__hold__tns": { - "value": 0.0, + "value": -1.2, "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 19283, + "value": 21354, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -76,23 +80,23 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -0.3, "compare": ">=" }, "finish__timing__setup__tns": { - "value": 0.0, + "value": -1.2, "compare": ">=" }, "finish__timing__hold__ws": { - "value": 0.0, + "value": -0.3, "compare": ">=" }, "finish__timing__hold__tns": { - "value": 0.0, + "value": -1.2, "compare": ">=" }, "finish__design__instance__area": { - "value": 70862, + "value": 70132, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/src/aes/BUILD.bazel b/flow/designs/src/aes/BUILD.bazel index 3a5e9ed8a7..8ccd944700 100644 --- a/flow/designs/src/aes/BUILD.bazel +++ b/flow/designs/src/aes/BUILD.bazel @@ -5,6 +5,6 @@ exports_files( filegroup( name = "verilog", - srcs = glob(include = ["*.v"]), + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), visibility = ["//visibility:public"], ) diff --git a/flow/designs/src/ethmac/BUILD.bazel b/flow/designs/src/ethmac/BUILD.bazel index 3a5e9ed8a7..8ccd944700 100644 --- a/flow/designs/src/ethmac/BUILD.bazel +++ b/flow/designs/src/ethmac/BUILD.bazel @@ -5,6 +5,6 @@ exports_files( filegroup( name = "verilog", - srcs = glob(include = ["*.v"]), + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), visibility = ["//visibility:public"], ) diff --git a/flow/designs/src/gcd/BUILD.bazel b/flow/designs/src/gcd/BUILD.bazel index 3a5e9ed8a7..8ccd944700 100644 --- a/flow/designs/src/gcd/BUILD.bazel +++ b/flow/designs/src/gcd/BUILD.bazel @@ -5,6 +5,6 @@ exports_files( filegroup( name = "verilog", - srcs = glob(include = ["*.v"]), + srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), visibility = ["//visibility:public"], ) From f4d1ee80d96d9dfb1f140f33d7cbb864915c9b78 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 21:30:24 +0200 Subject: [PATCH 03/28] docs: regenerate variables.json and FlowVariables.md MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Run yaml_to_json.py and generate-variables-docs.py so the generated artifacts match the new entries added to variables.yaml in the bazel-orfs beta-test commit. Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 24 +++++++++++++++++++ flow/scripts/variables.json | 48 +++++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 80d3073bc5..2cb00d66d9 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -173,6 +173,7 @@ configuration file. | LEC_AUX_VERILOG_FILES| Additional Verilog files (e.g. blackbox stubs) to include in LEC equivalence checks. Appended to the generated Verilog netlist before running the formal equivalence check.| | | LEC_CHECK| Perform a formal equivalence check between before and after netlists. If this fails, report an issue to OpenROAD.| 0| | LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| | +| LIB_MODEL| Selects the standard cell library timing model. Set to CCS to use composite current source liberty files; default selects the NLDM (non-linear delay model) variant.| | | MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| | | MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| | | MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place macros manually. The user may choose to place just some of the macros in the design. The macro placer will handle the remaining unplaced macros.| | @@ -188,8 +189,11 @@ configuration file. | MAX_REPAIR_TIMING_ITER| Maximum number of iterations for repair setup and repair hold.| | | MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| | | MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| | +| MIN_CLK_ROUTING_LAYER| Lowest metal layer that clock tree synthesis may use for clock routing. Mirrors MIN_ROUTING_LAYER but applies to clock nets.| | | MIN_PLACE_STEP_COEF| Sets the minimum phi coefficient (pcof_min / µ_k Lower Bound) for global placement optimization. This parameter controls the step size lower bound in the RePlAce Nesterov optimization algorithm. Lower values may improve convergence but can increase runtime. Valid range: 0.95-1.05| 0.95| | MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| | +| MOCK_ALU_OPERATIONS| Comma-separated list of ALU operations baked into the generated mock-alu RTL (e.g. ADD,SUB,AND). Consumed by the Chisel generator in src/mock-alu.| | +| MOCK_ALU_WIDTH| Datapath width in bits for the generated mock-alu RTL. Consumed by the Chisel generator in src/mock-alu.| | | NUM_CORES| Passed to `openroad -threads $(NUM_CORES)`, defaults to numbers of cores in system as determined by system specific code in Makefile, `nproc` is tried first. OpenROAD does not limit itself to this number of cores across OpenROAD running instances, which can lead to overprovisioning in contexts such as bazel-orfs where there could be many routing, or place jobs running at the same time.| | | OPENROAD_HIERARCHICAL| Feature toggle to enable to run OpenROAD in hierarchical mode, otherwise considered flat. Will eventually be the default and this option will be retired.| 0| | OR_K| Passed as -or_k to detailed routing.| | @@ -266,6 +270,7 @@ configuration file. | RUN_SCRIPT| Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.| | | SC_LEF| Path to technology standard cell LEF file.| | | SDC_FILE| The path to design constraint (SDC) file.| | +| SDC_FILE_EXTRA| Path to an additional Tcl file sourced from constraint.sdc and from place_pins I/O scripts. Used by designs that share helper Tcl between SDC and pin placement (e.g. mock-cpu).| | | SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | SEAL_GDS| Seal macro to place around the design.| | | SETUP_MOVE_SEQUENCE| Passed as -sequence to repair_timing. This should be a string of move keywords separated by commas.| | @@ -303,6 +308,7 @@ configuration file. | SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0| | SYNTH_MOCK_LARGE_MEMORIES| Reduce Yosys inferred memories larger than SYNTH_MEMORY_MAX_BITS to 1 row. Yosys will generally infer memories from behavioral Verilog code, whether the memories are in standalone modules or instantiated within some larger module. fakeram and empty Verilog memories(blackboxes) of memories will not be inferred memories by Yosys and are therefore not affected by this variable. This is useful and convenient to separate the concern of instantiating and placing memories from investigating other issues with a design, though it comes at the expense of the increased accuracy that using realistic fakemem would provide. Memories with a single 1 row will of course have unrealistically good timing and area characteristics, but timing will still correctly terminate in a register. Large port memories, typically register files, will still have the retain a lot of the port logic that can be useful to investigate issues. This can be especially useful during development of designs where the behavioral model comes first and suitable memories are matched up when the design RTL is stable. A typical use case would be Chisel which will generate a behavioral model for a memories with the required clocks, ports, etc. in addition to a computer readable file with the specification of the memories that is used to [automatically](https://chipyard.readthedocs.io/en/stable/Tools/Barstools.html/) match up suitable memory macros later in the flow. During an architectural screening study, a large range of memory configurations can be investigated quickly with this option, without getting bogged down in the concern of how to realize the memories in silicon for emphemral RTL configurations that exist only long enough to run through the ORFS flow to create a table of some characteristics of a design configuration.| 0| | SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | +| SYNTH_NUM_PARTITIONS| Total number of partitions used by the parallel synthesis flow. Set automatically by bazel-orfs based on SYNTH_KEEP_MODULES; not typically set by users.| | | SYNTH_OPERATIONS_ARGS| Extra arguments appended to the Yosys synth command operations list. When set, replaces the default Kogge-Stone adder extra-map.| | | SYNTH_OPT_HIER| Optimize constants across hierarchical boundaries.| | | SYNTH_REPEATABLE_BUILD| License to prune anything that makes builds less repeatable, typically used with Bazel to ensure that builds are bit-for-bit identical so that caching works optimally. Removes debug information that encodes paths, timestamps, etc.| 0| @@ -342,10 +348,14 @@ configuration file. - [DFF_LIB_FILE](#DFF_LIB_FILE) - [DFF_MAP_FILE](#DFF_MAP_FILE) - [LATCH_MAP_FILE](#LATCH_MAP_FILE) +- [LIB_MODEL](#LIB_MODEL) - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS) +- [MOCK_ALU_OPERATIONS](#MOCK_ALU_OPERATIONS) +- [MOCK_ALU_WIDTH](#MOCK_ALU_WIDTH) - [POST_SYNTH_TCL](#POST_SYNTH_TCL) - [PRE_SYNTH_TCL](#PRE_SYNTH_TCL) - [SDC_FILE](#SDC_FILE) +- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SDC_GUT](#SDC_GUT) - [SLANG_PLUGIN_PATH](#SLANG_PLUGIN_PATH) - [SYNTH_ARGS](#SYNTH_ARGS) @@ -363,6 +373,7 @@ configuration file. - [SYNTH_MINIMUM_KEEP_SIZE](#SYNTH_MINIMUM_KEEP_SIZE) - [SYNTH_MOCK_LARGE_MEMORIES](#SYNTH_MOCK_LARGE_MEMORIES) - [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES) +- [SYNTH_NUM_PARTITIONS](#SYNTH_NUM_PARTITIONS) - [SYNTH_OPERATIONS_ARGS](#SYNTH_OPERATIONS_ARGS) - [SYNTH_OPT_HIER](#SYNTH_OPT_HIER) - [SYNTH_REPEATABLE_BUILD](#SYNTH_REPEATABLE_BUILD) @@ -394,6 +405,7 @@ configuration file. - [FOOTPRINT_TCL](#FOOTPRINT_TCL) - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) - [IO_CONSTRAINTS](#IO_CONSTRAINTS) +- [LIB_MODEL](#LIB_MODEL) - [MACRO_BLOCKAGE_HALO](#MACRO_BLOCKAGE_HALO) - [MACRO_PLACEMENT_TCL](#MACRO_PLACEMENT_TCL) - [MACRO_PLACE_HALO](#MACRO_PLACE_HALO) @@ -436,6 +448,7 @@ configuration file. - [RTLMP_OUTLINE_WT](#RTLMP_OUTLINE_WT) - [RTLMP_RPT_DIR](#RTLMP_RPT_DIR) - [RTLMP_WIRELENGTH_WT](#RTLMP_WIRELENGTH_WT) +- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SETUP_MOVE_SEQUENCE](#SETUP_MOVE_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_BUFFER_REMOVAL](#SKIP_BUFFER_REMOVAL) @@ -470,6 +483,7 @@ configuration file. - [GPL_TIMING_DRIVEN](#GPL_TIMING_DRIVEN) - [IO_PLACER_H](#IO_PLACER_H) - [IO_PLACER_V](#IO_PLACER_V) +- [LIB_MODEL](#LIB_MODEL) - [MATCH_CELL_FOOTPRINT](#MATCH_CELL_FOOTPRINT) - [MAX_PLACE_STEP_COEF](#MAX_PLACE_STEP_COEF) - [MAX_REPAIR_TIMING_ITER](#MAX_REPAIR_TIMING_ITER) @@ -492,6 +506,7 @@ configuration file. - [PRE_REPAIR_TIMING_POST_PLACE_TCL](#PRE_REPAIR_TIMING_POST_PLACE_TCL) - [PRE_RESIZE_TCL](#PRE_RESIZE_TCL) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TNS_END_PERCENT](#TNS_END_PERCENT) @@ -510,11 +525,14 @@ configuration file. - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) - [LEC_AUX_VERILOG_FILES](#LEC_AUX_VERILOG_FILES) - [LEC_CHECK](#LEC_CHECK) +- [LIB_MODEL](#LIB_MODEL) - [MATCH_CELL_FOOTPRINT](#MATCH_CELL_FOOTPRINT) - [MAX_REPAIR_TIMING_ITER](#MAX_REPAIR_TIMING_ITER) +- [MIN_CLK_ROUTING_LAYER](#MIN_CLK_ROUTING_LAYER) - [POST_CTS_TCL](#POST_CTS_TCL) - [PRE_CTS_TCL](#PRE_CTS_TCL) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) +- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SETUP_MOVE_SEQUENCE](#SETUP_MOVE_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_BUFFER_REMOVAL](#SKIP_BUFFER_REMOVAL) @@ -534,6 +552,7 @@ configuration file. - [ENABLE_RESISTANCE_AWARE](#ENABLE_RESISTANCE_AWARE) - [GLOBAL_ROUTE_ARGS](#GLOBAL_ROUTE_ARGS) - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) +- [LIB_MODEL](#LIB_MODEL) - [MAX_REPAIR_ANTENNAS_ITER_GRT](#MAX_REPAIR_ANTENNAS_ITER_GRT) - [MAX_REPAIR_TIMING_ITER](#MAX_REPAIR_TIMING_ITER) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) @@ -542,6 +561,7 @@ configuration file. - [PRE_GLOBAL_ROUTE_TCL](#PRE_GLOBAL_ROUTE_TCL) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SETUP_MOVE_SEQUENCE](#SETUP_MOVE_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_ANTENNA_REPAIR](#SKIP_ANTENNA_REPAIR) @@ -564,6 +584,7 @@ configuration file. - [DETAILED_ROUTE_END_ITERATION](#DETAILED_ROUTE_END_ITERATION) - [DISABLE_VIA_GEN](#DISABLE_VIA_GEN) - [FILL_CELLS](#FILL_CELLS) +- [LIB_MODEL](#LIB_MODEL) - [MATCH_CELL_FOOTPRINT](#MATCH_CELL_FOOTPRINT) - [MAX_REPAIR_ANTENNAS_ITER_DRT](#MAX_REPAIR_ANTENNAS_ITER_DRT) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) @@ -576,6 +597,7 @@ configuration file. - [PRE_FILLCELL_TCL](#PRE_FILLCELL_TCL) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SKIP_ANTENNA_REPAIR_POST_DRT](#SKIP_ANTENNA_REPAIR_POST_DRT) - [SKIP_DETAILED_ROUTE](#SKIP_DETAILED_ROUTE) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) @@ -588,6 +610,7 @@ configuration file. - [CDL_FILE](#CDL_FILE) - [GDS_ALLOW_EMPTY](#GDS_ALLOW_EMPTY) - [GND_NETS_VOLTAGES](#GND_NETS_VOLTAGES) +- [LIB_MODEL](#LIB_MODEL) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) - [POST_DENSITY_FILL_TCL](#POST_DENSITY_FILL_TCL) @@ -597,6 +620,7 @@ configuration file. - [PWR_NETS_VOLTAGES](#PWR_NETS_VOLTAGES) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) +- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SKIP_DETAILED_ROUTE](#SKIP_DETAILED_ROUTE) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) diff --git a/flow/scripts/variables.json b/flow/scripts/variables.json index 0c8e56ad77..392cd30d25 100644 --- a/flow/scripts/variables.json +++ b/flow/scripts/variables.json @@ -483,6 +483,18 @@ "LIB_FILES": { "description": "A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.\n" }, + "LIB_MODEL": { + "description": "Selects the standard cell library timing model. Set to CCS to use composite current source liberty files; default selects the NLDM (non-linear delay model) variant.\n", + "stages": [ + "synth", + "floorplan", + "place", + "cts", + "grt", + "route", + "final" + ] + }, "MACRO_BLOCKAGE_HALO": { "description": "Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.\n", "stages": [ @@ -586,6 +598,12 @@ "synth" ] }, + "MIN_CLK_ROUTING_LAYER": { + "description": "Lowest metal layer that clock tree synthesis may use for clock routing. Mirrors MIN_ROUTING_LAYER but applies to clock nets.\n", + "stages": [ + "cts" + ] + }, "MIN_PLACE_STEP_COEF": { "default": 0.95, "description": "Sets the minimum phi coefficient (pcof_min / \u00b5_k Lower Bound) for global placement optimization. This parameter controls the step size lower bound in the RePlAce Nesterov optimization algorithm. Lower values may improve convergence but can increase runtime. Valid range: 0.95-1.05\n", @@ -605,6 +623,18 @@ "final" ] }, + "MOCK_ALU_OPERATIONS": { + "description": "Comma-separated list of ALU operations baked into the generated mock-alu RTL (e.g. ADD,SUB,AND). Consumed by the Chisel generator in src/mock-alu.\n", + "stages": [ + "synth" + ] + }, + "MOCK_ALU_WIDTH": { + "description": "Datapath width in bits for the generated mock-alu RTL. Consumed by the Chisel generator in src/mock-alu.\n", + "stages": [ + "synth" + ] + }, "NUM_CORES": { "description": "Passed to `openroad -threads $(NUM_CORES)`, defaults to numbers of cores in system as determined by system specific code in Makefile, `nproc` is tried first. OpenROAD does not limit itself to this number of cores across OpenROAD running instances, which can lead to overprovisioning in contexts such as bazel-orfs where there could be many routing, or place jobs running at the same time.\n", "stages": [ @@ -1065,6 +1095,18 @@ "synth" ] }, + "SDC_FILE_EXTRA": { + "description": "Path to an additional Tcl file sourced from constraint.sdc and from place_pins I/O scripts. Used by designs that share helper Tcl between SDC and pin placement (e.g. mock-cpu).\n", + "stages": [ + "synth", + "floorplan", + "place", + "cts", + "grt", + "route", + "final" + ] + }, "SDC_GUT": { "description": "Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.\n", "stages": [ @@ -1320,6 +1362,12 @@ "synth" ] }, + "SYNTH_NUM_PARTITIONS": { + "description": "Total number of partitions used by the parallel synthesis flow. Set automatically by bazel-orfs based on SYNTH_KEEP_MODULES; not typically set by users.\n", + "stages": [ + "synth" + ] + }, "SYNTH_OPERATIONS_ARGS": { "description": "Extra arguments appended to the Yosys synth command operations list. When set, replaces the default Kogge-Stone adder extra-map.\n", "stages": [ From 367e0c18570c31dcf2f242fb86e31730272d7914 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 21:32:19 +0200 Subject: [PATCH 04/28] docs: condense bazel-orfs.md MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop the early-version framing, per-platform design lists (discoverable via bazelisk query), known-failure inventory (rots fast), and the "workflow / unmerged commits" prose. Keep target conventions, how to add a design, local override, --jobs caveat, and the non-public PDK note. Signed-off-by: Øyvind Harboe --- bazel-orfs.md | 307 +++++++------------------------------------------- 1 file changed, 43 insertions(+), 264 deletions(-) diff --git a/bazel-orfs.md b/bazel-orfs.md index 5b7f80629a..c183788941 100644 --- a/bazel-orfs.md +++ b/bazel-orfs.md @@ -1,168 +1,40 @@ -# bazel-orfs Beta Test +# bazel-orfs -This is an early integration of [bazel-orfs](https://github.com/The-OpenROAD-Project/bazel-orfs) -into OpenROAD-flow-scripts. It lets you build ORFS designs with Bazel -using the same `config.mk` files you already have. +Bazel front-end for the ORFS Make flow. Designs declared via +`config.mk` are exposed as Bazel targets through +[bazel-orfs](https://github.com/The-OpenROAD-Project/bazel-orfs). -**Status**: beta -- 59 designs across 6 public PDK platforms have -`orfs_design()` enabled. 53 pass QoR tests; 6 designs are blocked on -upstream fixes (see below). Platforms without public PDK files (gf12, -gf55, rapidus2hp) are not wired up. +## Targets -## Quick Start +For a design at `flow/designs///` with `DESIGN_NAME = +`: -```bash -# Install bazelisk (one-time) -- see https://github.com/bazelbuild/bazelisk -# Then, from the ORFS root: +| Target | Output | +|---|---| +| `_synth` | Yosys synthesis | +| `_floorplan` | Floorplan + I/O placement | +| `_place` | Placement | +| `_cts` | Clock tree synthesis | +| `_grt` | Global routing | +| `_route` | Detailed routing | +| `_final` | Final + fill | +| `_generate_abstract` | LEF/LIB abstract | +| `_test` | Full flow + QoR check against `rules-base.json` | +| `_update` | Rebuild and write thresholds back to `rules-base.json` | + +Stages depend on the previous, so `_final` runs the whole flow. -# Synthesize gcd on asap7 (downloads Docker image on first run) +```bash bazelisk build //flow/designs/asap7/gcd:gcd_synth - -# Run through floorplan -bazelisk build //flow/designs/asap7/gcd:gcd_floorplan - -# Full flow through final -bazelisk build //flow/designs/asap7/gcd:gcd_final - -# Run the test (includes QoR regression check) -bazelisk test //flow/designs/asap7/gcd:gcd_test - -# List all targets for a design -bazelisk query //flow/designs/asap7/gcd:all +bazelisk test //flow/designs/asap7/gcd:gcd_test +bazelisk run //flow/designs/asap7/gcd:gcd_update +bazelisk query //flow/designs/asap7/...:* ``` -## Available Targets Per Design - -Each enabled design gets these targets automatically from its `config.mk`: - -| Target suffix | What it does | -|---|---| -| `_synth` | Yosys synthesis | -| `_floorplan` | Floorplan + I/O placement | -| `_place` | Global + detailed placement | -| `_cts` | Clock tree synthesis | -| `_grt` | Global routing | -| `_route` | Detailed routing | -| `_final` | Final optimization + fill | -| `_generate_abstract` | LEF/LIB abstract for hierarchical use | -| `_generate_metadata` | Flow metadata (logs, reports) | -| `_test` | Full flow + QoR regression check | - -Each stage depends on the previous one, so building `_final` runs the -entire flow. - -## Working Designs (53 passing tests + 6 blocked) - -All designs below have `orfs_design()` enabled. Designs marked -**(blocked)** fail due to upstream issues in bazel-orfs or the -design's verilog sources. - -### asap7 (18 designs) - -| Design | DESIGN_NAME | Notes | -|--------|-------------|-------| -| `gcd` | gcd | smoketest, ~1 min | -| `gcd-ccs` | gcd | CCS lib model | -| `aes` | aes_cipher_top | medium | -| `aes-block` | aes_cipher_top | block variant | -| `aes-mbff` | aes_cipher_top | MBFF | -| `aes_lvt` | aes_cipher_top | LVT cells | -| `ethmac` | ethmac | Ethernet MAC | -| `ethmac_lvt` | ethmac | LVT cells | -| `ibex` | ibex_core | RISC-V core (slang) | -| `jpeg` | jpeg_encoder | JPEG encoder | -| `jpeg_lvt` | jpeg_encoder | LVT cells | -| `uart` | uart | UART | -| `riscv32i` | riscv_top | RISC-V RV32I | -| `riscv32i-mock-sram` | riscv_top | **(blocked)** PSM-0069 VDD connectivity | -| `mock-cpu` | mock_cpu | mock CPU with FIFO | -| `swerv_wrapper` | swerv_wrapper | SweRV EH1 | -| `cva6` | cva6 | CVA6 RISC-V (~63 min) | -| `mock-alu` | MockAlu | mock ALU | - -### sky130hd (7 designs) - -| Design | DESIGN_NAME | Notes | -|--------|-------------|-------| -| `gcd` | gcd | smoketest | -| `aes` | aes_cipher_top | medium | -| `ibex` | ibex_core | RISC-V core | -| `jpeg` | jpeg_encoder | JPEG encoder | -| `riscv32i` | riscv | RISC-V RV32I | -| `chameleon` | soc_core | SoC with macros | -| `microwatt` | microwatt | POWER ISA core | - -### nangate45 (16 designs) - -| Design | DESIGN_NAME | Notes | -|--------|-------------|-------| -| `gcd` | gcd | smoketest | -| `aes` | aes_cipher_top | medium | -| `ibex` | ibex_core | RISC-V core | -| `jpeg` | jpeg_encoder | JPEG encoder | -| `dynamic_node` | dynamic_node_top_wrap | NoC router | -| `swerv` | swerv | SweRV EH1 | -| `tinyRocket` | RocketTile | RISC-V Rocket | -| `ariane133` | ariane | hierarchical | -| `ariane136` | ariane | hierarchical | -| `black_parrot` | black_parrot | **(blocked)** MPL-0020 macro name mismatch | -| `bp_be_top` | bp_be_top | BP back-end | -| `bp_fe_top` | bp_fe_top | BP front-end | -| `bp_multi_top` | bp_multi_top | **(blocked)** OpenROAD crash in CTS | -| `bp_quad` | black_parrot | **(blocked)** yosys check -assert fails | -| `mempool_group` | mempool_group | **(blocked)** SV macro undefined in synth | -| `swerv_wrapper` | swerv_wrapper | SweRV wrapped | - -### gf180 (6 designs) - -| Design | DESIGN_NAME | Notes | -|--------|-------------|-------| -| `aes` | aes_cipher_top | medium | -| `aes-hybrid` | aes_cipher_top | hybrid variant | -| `ibex` | ibex_core | RISC-V core | -| `jpeg` | jpeg_encoder | JPEG encoder | -| `riscv32i` | riscv | RISC-V RV32I | -| `uart-blocks` | uart | hierarchical with uart_rx block | - -### ihp-sg13g2 (7 designs) - -| Design | DESIGN_NAME | Notes | -|--------|-------------|-------| -| `gcd` | gcd | smoketest | -| `aes` | aes_cipher_top | medium | -| `ibex` | ibex_core | RISC-V core | -| `jpeg` | jpeg_encoder | JPEG encoder | -| `riscv32i` | riscv | RISC-V RV32I | -| `spi` | spi | SPI controller | -| `i2c-gpio-expander` | I2cGpioExpanderTop | **(blocked)** PAD-0102 IO pad instance not found | - -### sky130hs (5 designs) - -| Design | DESIGN_NAME | Notes | -|--------|-------------|-------| -| `gcd` | gcd | smoketest | -| `aes` | aes_cipher_top | medium | -| `ibex` | ibex_core | RISC-V core | -| `jpeg` | jpeg_encoder | JPEG encoder | -| `riscv32i` | riscv | RISC-V RV32I | - -## Designs Not Supported - -### No VERILOG_FILES (minimal) - -`asap7/minimal` is a test design with no `VERILOG_FILES` in config.mk -(empty SDC). Not expected to work with `orfs_designs`. - -### Platforms without public PDK - -gf12, gf55, and rapidus2hp have design directories but no platform -files in the open-source repo. These are skipped entirely. - -## How to Add More Designs - -1. Create `flow/designs///BUILD.bazel`: +## Adding a design ```starlark +# flow/designs///BUILD.bazel load("@bazel-orfs//:openroad.bzl", "orfs_design") load("@orfs_designs//:designs.bzl", "DESIGNS") @@ -171,122 +43,29 @@ exports_files(glob(["*"])) orfs_design(designs = DESIGNS) ``` -2. If `flow/designs/src//BUILD.bazel` doesn't exist, create it: +If `flow/designs/src//BUILD.bazel` is missing, add: ```starlark -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) - -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +exports_files(glob(["*.v", "*.sv"], allow_empty = True), visibility = ["//visibility:public"]) +filegroup(name = "verilog", srcs = glob(["*.v", "*.sv"], allow_empty = True), visibility = ["//visibility:public"]) ``` -3. Run `bazelisk query //flow/designs//:all` to verify. - -## Using a Local bazel-orfs Checkout - -To iterate on bazel-orfs rules locally, replace the `git_override` in -`MODULE.bazel`: - -```starlark -# Comment out the git_override block, then add: -local_path_override( - module_name = "bazel-orfs", - path = "/path/to/your/bazel-orfs", -) -``` - -Also update the `bazel-orfs-verilog` override: - -```starlark -local_path_override( - module_name = "bazel-orfs-verilog", - path = "/path/to/your/bazel-orfs/verilog", -) -``` - -## Key Differences from Make - -- **Incremental**: Bazel caches every stage. Changing `PLACE_DENSITY` - in `config.mk` rebuilds only floorplan onward -- synthesis is cached. -- **Hermetic**: Tools come from a Docker image (extracted automatically). - No `make install` or `PATH` setup needed. -- **Parallel**: Independent designs build in parallel automatically. -- **Reproducible**: Same inputs always produce the same outputs. - -## Performance Notes - -Each OpenROAD invocation uses `-threads ` (all available cores). -When Bazel runs many designs in parallel, the machine becomes heavily -overcommitted. On a 48-core machine, 50+ OpenROAD instances may run -simultaneously during a full `bazelisk test ...`, each requesting 48 -threads. - -To limit parallelism: - -```bash -# Limit to 4 concurrent OpenROAD invocations -bazelisk test --jobs=4 ... -``` - -A full test suite run (53 designs, 6 platforms) takes roughly 4-5 hours -on a 48-core machine with default parallelism (overcommitted). Individual -design times vary from ~1 minute (gcd) to ~63 minutes (cva6 on asap7). - -## Updating Metric Thresholds - -When OpenROAD or flow scripts change, metric thresholds in -`rules-base.json` may go stale. To update them for a specific design: - -```bash -# Rebuilds the design and writes updated thresholds back to source -bazelisk run //flow/designs/asap7/aes-block:aes_cipher_top_update -``` - -The target name follows the pattern `_update` where -`` comes from `DESIGN_NAME` in `config.mk`. - -## Equivalence Checking (eqy) +A design counts as CI-tested iff `rules-base.json` exists; without it +the generated targets get `tags = ["manual"]`. -Some designs (e.g. `aes`) set `EQUIVALENCE_CHECK=1` in their -`config.mk` to enable equivalence checking of repair_timing. The -actual `eqy` tool invocation is gated by a separate `RUN_EQY` -variable (default 0), so builds don't fail when eqy is not installed. -CI sets `RUN_EQY=1` when eqy is available. +## Local bazel-orfs -## Workflow: Unmerged Commits +Replace the `git_override` for `bazel-orfs` and `bazel-orfs-verilog` in +`MODULE.bazel` with `local_path_override` pointing at the checkout +(and `…/verilog` for the latter). -This PR serves as a working branch against master. Commits here are -spun off as separate, focused PRs for review. Once a PR merges, this -branch is rebased on master to drop the merged commit. The branch is -force-pushed after each rebase so the PR commit list is always the -source of truth for what's pending. +## Parallelism -Filing of PRs is throttled to avoid overwhelming maintainers -- -submitting too many at once just causes "maintainer packet dropping" -where reviews stall. +Each OpenROAD invocation takes `-threads `. A wildcard +`bazelisk test` runs designs in parallel and overcommits the host. Cap +with `--jobs=N`. -## Known Limitations +## Non-public PDKs -- The Docker image is pinned; updating it requires changing - `MODULE.bazel`. -- Platforms without public PDK files (gf12, gf55, rapidus2hp) are not - supported. -- **black_parrot**: macro_placement.tcl references macro names that - don't match the synthesized netlist (MPL-0020). -- **bp_multi_top**: OpenROAD crashes (SIGSEGV) during CTS timing - analysis. -- **bp_quad**: yosys `check -assert` finds 9 problems during synthesis. -- **i2c-gpio-expander**: IO pad instance `sg13g2_IOPad_io_gpio_3` not - found during floorplan (PAD-0102). -- **mempool_group**: SystemVerilog macros (`AXI_TYPEDEF_RESP_T` etc.) - are undefined -- likely a missing include path in the bazel build. -- **riscv32i-mock-sram**: VDD connectivity check fails at final stage - (PSM-0069) -- fakeram macro power pins are unconnected. -- This is a beta -- expect rough edges. File issues at - https://github.com/The-OpenROAD-Project/bazel-orfs/issues +`gf12`, `gf55`, `rapidus2hp` are not wired up; their platform files +are not in this repo. From cc6dcc8648814edc8294ae518bb138dcd5d50413 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 21:32:34 +0200 Subject: [PATCH 05/28] build: bazelignore gf12 and gf55 design dirs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Their platform files are not in this repo, so the auto-generated orfs_design() targets would not resolve. Excluding them here keeps wildcard queries and globs clean. Signed-off-by: Øyvind Harboe --- .bazelignore | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.bazelignore b/.bazelignore index 7bfdcf03d8..0ad0424a9c 100644 --- a/.bazelignore +++ b/.bazelignore @@ -5,4 +5,8 @@ etc/ jenkins/ docs/ +# Non-public PDKs: design dirs without matching flow/platforms// +flow/designs/gf12/ +flow/designs/gf55/ + From fb239f559951e850d91f45c61cde0b565b03542d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 21:34:46 +0200 Subject: [PATCH 06/28] fix: drop gf12/gf55 entries from .bazelignore MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The security pre-commit hook blocks the names. The directories have no BUILD.bazel files and orfs_designs doesn't list those platforms, so they're already excluded from the bazel build. Signed-off-by: Øyvind Harboe --- .bazelignore | 4 ---- 1 file changed, 4 deletions(-) diff --git a/.bazelignore b/.bazelignore index 0ad0424a9c..7bfdcf03d8 100644 --- a/.bazelignore +++ b/.bazelignore @@ -5,8 +5,4 @@ etc/ jenkins/ docs/ -# Non-public PDKs: design dirs without matching flow/platforms// -flow/designs/gf12/ -flow/designs/gf55/ - From d1e4f85879187175c2045c87cc46416749b987e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 21:46:37 +0200 Subject: [PATCH 07/28] build: factor out BUILD.bazel boilerplate via flow/designs/design.bzl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce design() and files() macros in flow/designs/design.bzl so each per-design BUILD shrinks to two lines. The bazelisk //flow/designs//:_test interface is unchanged. Drop the Non-public PDKs section from bazel-orfs.md (security hook blocks the names; auto-generation already only scans the platforms listed in MODULE.bazel). Signed-off-by: Øyvind Harboe --- bazel-orfs.md | 5 --- flow/designs/asap7/aes-block/BUILD.bazel | 7 ++-- flow/designs/asap7/aes-mbff/BUILD.bazel | 7 ++-- flow/designs/asap7/aes/BUILD.bazel | 7 ++-- flow/designs/asap7/aes_lvt/BUILD.bazel | 7 ++-- flow/designs/asap7/cva6/BUILD.bazel | 8 ++--- flow/designs/asap7/ethmac/BUILD.bazel | 7 ++-- flow/designs/asap7/ethmac_lvt/BUILD.bazel | 7 ++-- flow/designs/asap7/gcd-ccs/BUILD.bazel | 7 ++-- flow/designs/asap7/gcd/BUILD.bazel | 7 ++-- flow/designs/asap7/ibex/BUILD.bazel | 8 ++--- flow/designs/asap7/jpeg/BUILD.bazel | 8 ++--- flow/designs/asap7/jpeg_lvt/BUILD.bazel | 8 ++--- flow/designs/asap7/mock-alu/BUILD.bazel | 7 ++-- flow/designs/asap7/mock-cpu/BUILD.bazel | 8 ++--- .../asap7/riscv32i-mock-sram/BUILD.bazel | 8 ++--- .../fakeram7_256x32/BUILD.bazel | 7 ++-- flow/designs/asap7/riscv32i/BUILD.bazel | 8 ++--- flow/designs/asap7/swerv_wrapper/BUILD.bazel | 8 ++--- .../asap7/swerv_wrapper/lef/BUILD.bazel | 11 ++---- .../asap7/swerv_wrapper/lib/BUILD.bazel | 11 ++---- flow/designs/asap7/uart/BUILD.bazel | 8 ++--- flow/designs/design.bzl | 34 +++++++++++++++++++ flow/designs/gf180/aes-hybrid/BUILD.bazel | 8 ++--- flow/designs/gf180/aes/BUILD.bazel | 8 ++--- flow/designs/gf180/ibex/BUILD.bazel | 8 ++--- flow/designs/gf180/jpeg/BUILD.bazel | 8 ++--- flow/designs/gf180/riscv32i/BUILD.bazel | 8 ++--- flow/designs/gf180/uart-blocks/BUILD.bazel | 7 ++-- .../gf180/uart-blocks/uart_rx/BUILD.bazel | 7 ++-- flow/designs/ihp-sg13g2/aes/BUILD.bazel | 8 ++--- flow/designs/ihp-sg13g2/gcd/BUILD.bazel | 8 ++--- .../ihp-sg13g2/i2c-gpio-expander/BUILD.bazel | 7 ++-- .../I2cDeviceCtrl/BUILD.bazel | 7 ++-- flow/designs/ihp-sg13g2/ibex/BUILD.bazel | 8 ++--- flow/designs/ihp-sg13g2/jpeg/BUILD.bazel | 8 ++--- flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel | 8 ++--- flow/designs/ihp-sg13g2/spi/BUILD.bazel | 8 ++--- flow/designs/nangate45/aes/BUILD.bazel | 8 ++--- flow/designs/nangate45/ariane133/BUILD.bazel | 7 ++-- flow/designs/nangate45/ariane136/BUILD.bazel | 7 ++-- .../nangate45/black_parrot/BUILD.bazel | 7 ++-- flow/designs/nangate45/bp_be_top/BUILD.bazel | 7 ++-- flow/designs/nangate45/bp_fe_top/BUILD.bazel | 7 ++-- .../nangate45/bp_multi_top/BUILD.bazel | 7 ++-- flow/designs/nangate45/bp_quad/BUILD.bazel | 7 ++-- .../nangate45/dynamic_node/BUILD.bazel | 8 ++--- flow/designs/nangate45/gcd/BUILD.bazel | 8 ++--- flow/designs/nangate45/ibex/BUILD.bazel | 8 ++--- flow/designs/nangate45/jpeg/BUILD.bazel | 8 ++--- .../nangate45/mempool_group/BUILD.bazel | 7 ++-- flow/designs/nangate45/swerv/BUILD.bazel | 8 ++--- .../nangate45/swerv_wrapper/BUILD.bazel | 7 ++-- flow/designs/nangate45/tinyRocket/BUILD.bazel | 8 ++--- flow/designs/sky130hd/aes/BUILD.bazel | 7 ++-- flow/designs/sky130hd/chameleon/BUILD.bazel | 8 ++--- .../sky130hd/chameleon/gds/BUILD.bazel | 11 ++---- .../sky130hd/chameleon/lef/BUILD.bazel | 11 ++---- flow/designs/sky130hd/gcd/BUILD.bazel | 7 ++-- flow/designs/sky130hd/ibex/BUILD.bazel | 8 ++--- flow/designs/sky130hd/jpeg/BUILD.bazel | 8 ++--- flow/designs/sky130hd/microwatt/BUILD.bazel | 8 ++--- .../sky130hd/microwatt/gds/BUILD.bazel | 11 ++---- .../sky130hd/microwatt/lef/BUILD.bazel | 11 ++---- .../sky130hd/microwatt/lib/BUILD.bazel | 11 ++---- flow/designs/sky130hd/riscv32i/BUILD.bazel | 8 ++--- flow/designs/sky130hs/aes/BUILD.bazel | 8 ++--- flow/designs/sky130hs/gcd/BUILD.bazel | 8 ++--- flow/designs/sky130hs/ibex/BUILD.bazel | 8 ++--- flow/designs/sky130hs/jpeg/BUILD.bazel | 8 ++--- flow/designs/sky130hs/riscv32i/BUILD.bazel | 8 ++--- flow/designs/src/aes/BUILD.bazel | 11 ++---- flow/designs/src/ariane/BUILD.bazel | 11 ++---- flow/designs/src/ariane133/BUILD.bazel | 11 ++---- flow/designs/src/ariane136/BUILD.bazel | 11 ++---- flow/designs/src/black_parrot/BUILD.bazel | 11 ++---- flow/designs/src/bp_be_top/BUILD.bazel | 11 ++---- flow/designs/src/bp_fe_top/BUILD.bazel | 11 ++---- flow/designs/src/bp_multi_top/BUILD.bazel | 11 ++---- flow/designs/src/bp_quad/BUILD.bazel | 11 ++---- .../chameleon/AHB_sys_0/APB_sys_0/BUILD.bazel | 11 ++---- .../src/chameleon/AHB_sys_0/BUILD.bazel | 11 ++---- flow/designs/src/chameleon/BUILD.bazel | 11 ++---- flow/designs/src/chameleon/IPs/BUILD.bazel | 11 ++---- .../src/chameleon/IPs/apb2i2c/BUILD.bazel | 11 ++---- flow/designs/src/chameleon/acc/BUILD.bazel | 11 ++---- flow/designs/src/chameleon/ibex/BUILD.bazel | 11 ++---- .../src/chameleon/ibex/models/BUILD.bazel | 11 ++---- flow/designs/src/coyote/BUILD.bazel | 11 ++---- flow/designs/src/cva6/BUILD.bazel | 11 ++---- flow/designs/src/cva6/common/BUILD.bazel | 11 ++---- .../designs/src/cva6/common/local/BUILD.bazel | 11 ++---- .../src/cva6/common/local/util/BUILD.bazel | 11 ++---- flow/designs/src/cva6/core/BUILD.bazel | 11 ++---- .../src/cva6/core/cache_subsystem/BUILD.bazel | 11 ++---- .../core/cache_subsystem/hpdcache/BUILD.bazel | 11 ++---- .../cache_subsystem/hpdcache/rtl/BUILD.bazel | 11 ++---- .../hpdcache/rtl/src/BUILD.bazel | 11 ++---- .../hpdcache/rtl/src/common/BUILD.bazel | 11 ++---- .../rtl/src/common/macros/BUILD.bazel | 11 ++---- .../src/common/macros/blackbox/BUILD.bazel | 11 ++---- .../hpdcache/rtl/src/hwpf_stride/BUILD.bazel | 11 ++---- .../hpdcache/rtl/src/utils/BUILD.bazel | 11 ++---- .../src/cva6/core/cva6_mmu/BUILD.bazel | 11 ++---- flow/designs/src/cva6/core/cvfpu/BUILD.bazel | 11 ++---- .../src/cva6/core/cvfpu/src/BUILD.bazel | 11 ++---- .../core/cvfpu/src/common_cells/BUILD.bazel | 11 ++---- .../cvfpu/src/fpu_div_sqrt_mvp/BUILD.bazel | 11 ++---- .../src/fpu_div_sqrt_mvp/hdl/BUILD.bazel | 11 ++---- .../src/cva6/core/cvxif_example/BUILD.bazel | 11 ++---- .../core/cvxif_example/include/BUILD.bazel | 11 ++---- .../src/cva6/core/frontend/BUILD.bazel | 11 ++---- flow/designs/src/cva6/core/pmp/BUILD.bazel | 11 ++---- .../designs/src/cva6/core/pmp/src/BUILD.bazel | 11 ++---- flow/designs/src/cva6/vendor/BUILD.bazel | 11 ++---- .../src/cva6/vendor/pulp-platform/BUILD.bazel | 11 ++---- .../cva6/vendor/pulp-platform/axi/BUILD.bazel | 11 ++---- .../vendor/pulp-platform/axi/src/BUILD.bazel | 11 ++---- .../pulp-platform/common_cells/BUILD.bazel | 11 ++---- .../common_cells/src/BUILD.bazel | 11 ++---- .../tech_cells_generic/BUILD.bazel | 11 ++---- .../tech_cells_generic/src/BUILD.bazel | 11 ++---- .../tech_cells_generic/src/rtl/BUILD.bazel | 11 ++---- flow/designs/src/dynamic_node/BUILD.bazel | 11 ++---- flow/designs/src/ethmac/BUILD.bazel | 11 ++---- flow/designs/src/fifo/BUILD.bazel | 11 ++---- flow/designs/src/gcd/BUILD.bazel | 11 ++---- flow/designs/src/ibex_sv/BUILD.bazel | 11 ++---- .../vendor/lowrisc_ip/prim/rtl/BUILD.bazel | 11 ++---- flow/designs/src/jpeg/BUILD.bazel | 11 ++---- flow/designs/src/mempool_group/BUILD.bazel | 11 ++---- flow/designs/src/microwatt/BUILD.bazel | 11 ++---- flow/designs/src/mock-alu/BUILD.bazel | 11 ++---- flow/designs/src/riscv32i/BUILD.bazel | 11 ++---- flow/designs/src/spi/BUILD.bazel | 11 ++---- flow/designs/src/swerv/BUILD.bazel | 11 ++---- flow/designs/src/tinyRocket/BUILD.bazel | 11 ++---- flow/designs/src/uart-no-param/BUILD.bazel | 11 ++---- flow/designs/src/uart/BUILD.bazel | 11 ++---- 139 files changed, 308 insertions(+), 1027 deletions(-) create mode 100644 flow/designs/design.bzl diff --git a/bazel-orfs.md b/bazel-orfs.md index c183788941..1e73a5f376 100644 --- a/bazel-orfs.md +++ b/bazel-orfs.md @@ -64,8 +64,3 @@ Replace the `git_override` for `bazel-orfs` and `bazel-orfs-verilog` in Each OpenROAD invocation takes `-threads `. A wildcard `bazelisk test` runs designs in parallel and overcommits the host. Cap with `--jobs=N`. - -## Non-public PDKs - -`gf12`, `gf55`, `rapidus2hp` are not wired up; their platform files -are not in this repo. diff --git a/flow/designs/asap7/aes-block/BUILD.bazel b/flow/designs/asap7/aes-block/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/asap7/aes-block/BUILD.bazel +++ b/flow/designs/asap7/aes-block/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/asap7/aes-mbff/BUILD.bazel b/flow/designs/asap7/aes-mbff/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/asap7/aes-mbff/BUILD.bazel +++ b/flow/designs/asap7/aes-mbff/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/asap7/aes/BUILD.bazel b/flow/designs/asap7/aes/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/asap7/aes/BUILD.bazel +++ b/flow/designs/asap7/aes/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/asap7/aes_lvt/BUILD.bazel b/flow/designs/asap7/aes_lvt/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/asap7/aes_lvt/BUILD.bazel +++ b/flow/designs/asap7/aes_lvt/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/asap7/cva6/BUILD.bazel b/flow/designs/asap7/cva6/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/asap7/cva6/BUILD.bazel +++ b/flow/designs/asap7/cva6/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/asap7/ethmac/BUILD.bazel b/flow/designs/asap7/ethmac/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/asap7/ethmac/BUILD.bazel +++ b/flow/designs/asap7/ethmac/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/asap7/ethmac_lvt/BUILD.bazel b/flow/designs/asap7/ethmac_lvt/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/asap7/ethmac_lvt/BUILD.bazel +++ b/flow/designs/asap7/ethmac_lvt/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/asap7/gcd-ccs/BUILD.bazel b/flow/designs/asap7/gcd-ccs/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/asap7/gcd-ccs/BUILD.bazel +++ b/flow/designs/asap7/gcd-ccs/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/asap7/gcd/BUILD.bazel b/flow/designs/asap7/gcd/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/asap7/gcd/BUILD.bazel +++ b/flow/designs/asap7/gcd/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/asap7/ibex/BUILD.bazel b/flow/designs/asap7/ibex/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/asap7/ibex/BUILD.bazel +++ b/flow/designs/asap7/ibex/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/asap7/jpeg/BUILD.bazel b/flow/designs/asap7/jpeg/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/asap7/jpeg/BUILD.bazel +++ b/flow/designs/asap7/jpeg/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/asap7/jpeg_lvt/BUILD.bazel b/flow/designs/asap7/jpeg_lvt/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/asap7/jpeg_lvt/BUILD.bazel +++ b/flow/designs/asap7/jpeg_lvt/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/asap7/mock-alu/BUILD.bazel b/flow/designs/asap7/mock-alu/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/asap7/mock-alu/BUILD.bazel +++ b/flow/designs/asap7/mock-alu/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/asap7/mock-cpu/BUILD.bazel b/flow/designs/asap7/mock-cpu/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/asap7/mock-cpu/BUILD.bazel +++ b/flow/designs/asap7/mock-cpu/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/asap7/riscv32i-mock-sram/BUILD.bazel b/flow/designs/asap7/riscv32i-mock-sram/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/asap7/riscv32i-mock-sram/BUILD.bazel +++ b/flow/designs/asap7/riscv32i-mock-sram/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel +++ b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/asap7/riscv32i/BUILD.bazel b/flow/designs/asap7/riscv32i/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/asap7/riscv32i/BUILD.bazel +++ b/flow/designs/asap7/riscv32i/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/asap7/swerv_wrapper/BUILD.bazel b/flow/designs/asap7/swerv_wrapper/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/asap7/swerv_wrapper/BUILD.bazel +++ b/flow/designs/asap7/swerv_wrapper/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/asap7/swerv_wrapper/lef/BUILD.bazel b/flow/designs/asap7/swerv_wrapper/lef/BUILD.bazel index 4419ddd7a3..14238a10ec 100644 --- a/flow/designs/asap7/swerv_wrapper/lef/BUILD.bazel +++ b/flow/designs/asap7/swerv_wrapper/lef/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.lef"]), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "lef", - srcs = glob(["*.lef"]), - visibility = ["//visibility:public"], -) +files("lef") diff --git a/flow/designs/asap7/swerv_wrapper/lib/BUILD.bazel b/flow/designs/asap7/swerv_wrapper/lib/BUILD.bazel index 5a1c76dc01..c477f56c5e 100644 --- a/flow/designs/asap7/swerv_wrapper/lib/BUILD.bazel +++ b/flow/designs/asap7/swerv_wrapper/lib/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.lib"]), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "lib", - srcs = glob(["*.lib"]), - visibility = ["//visibility:public"], -) +files("lib") diff --git a/flow/designs/asap7/uart/BUILD.bazel b/flow/designs/asap7/uart/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/asap7/uart/BUILD.bazel +++ b/flow/designs/asap7/uart/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/design.bzl b/flow/designs/design.bzl new file mode 100644 index 0000000000..64c2f7a27b --- /dev/null +++ b/flow/designs/design.bzl @@ -0,0 +1,34 @@ +"""BUILD.bazel boilerplate for flow/designs/.""" + +load("@bazel-orfs//:openroad.bzl", "orfs_design") +load("@orfs_designs//:designs.bzl", "DESIGNS") + +# Per filegroup target: (extensions in the filegroup, extensions in +# exports_files). bazel-orfs's config_mk_parser produces these target +# names from VERILOG_FILES wildcard patterns. +_GROUPS = { + "verilog": (["v", "sv"], ["v", "sv", "svh"]), + "include": (["v", "sv", "svh"], ["v", "sv", "svh"]), + "lef": (["lef"], ["lef"]), + "lib": (["lib"], ["lib"]), + "gds": (["gds", "gds.gz"], ["gds", "gds.gz"]), +} + +def design(): + """Standard BUILD body for flow/designs///.""" + native.exports_files(native.glob(["*"])) + orfs_design(designs = DESIGNS) + +def files(group, extra_srcs = None): + """Public exports_files + named filegroup over conventional extensions.""" + fg_exts, ex_exts = _GROUPS[group] + native.exports_files( + native.glob(["*.{}".format(e) for e in ex_exts], allow_empty = True), + visibility = ["//visibility:public"], + ) + native.filegroup( + name = group, + srcs = native.glob(["*.{}".format(e) for e in fg_exts], allow_empty = True) + + (extra_srcs or []), + visibility = ["//visibility:public"], + ) diff --git a/flow/designs/gf180/aes-hybrid/BUILD.bazel b/flow/designs/gf180/aes-hybrid/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/gf180/aes-hybrid/BUILD.bazel +++ b/flow/designs/gf180/aes-hybrid/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/gf180/aes/BUILD.bazel b/flow/designs/gf180/aes/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/gf180/aes/BUILD.bazel +++ b/flow/designs/gf180/aes/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/gf180/ibex/BUILD.bazel b/flow/designs/gf180/ibex/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/gf180/ibex/BUILD.bazel +++ b/flow/designs/gf180/ibex/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/gf180/jpeg/BUILD.bazel b/flow/designs/gf180/jpeg/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/gf180/jpeg/BUILD.bazel +++ b/flow/designs/gf180/jpeg/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/gf180/riscv32i/BUILD.bazel b/flow/designs/gf180/riscv32i/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/gf180/riscv32i/BUILD.bazel +++ b/flow/designs/gf180/riscv32i/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/gf180/uart-blocks/BUILD.bazel b/flow/designs/gf180/uart-blocks/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/gf180/uart-blocks/BUILD.bazel +++ b/flow/designs/gf180/uart-blocks/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel b/flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel +++ b/flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/ihp-sg13g2/aes/BUILD.bazel b/flow/designs/ihp-sg13g2/aes/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/ihp-sg13g2/aes/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/aes/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/ihp-sg13g2/gcd/BUILD.bazel b/flow/designs/ihp-sg13g2/gcd/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/ihp-sg13g2/gcd/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/gcd/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel b/flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/ihp-sg13g2/ibex/BUILD.bazel b/flow/designs/ihp-sg13g2/ibex/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/ihp-sg13g2/ibex/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/ibex/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/ihp-sg13g2/jpeg/BUILD.bazel b/flow/designs/ihp-sg13g2/jpeg/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/ihp-sg13g2/jpeg/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/jpeg/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel b/flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/ihp-sg13g2/spi/BUILD.bazel b/flow/designs/ihp-sg13g2/spi/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/ihp-sg13g2/spi/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/spi/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/nangate45/aes/BUILD.bazel b/flow/designs/nangate45/aes/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/nangate45/aes/BUILD.bazel +++ b/flow/designs/nangate45/aes/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/nangate45/ariane133/BUILD.bazel b/flow/designs/nangate45/ariane133/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/nangate45/ariane133/BUILD.bazel +++ b/flow/designs/nangate45/ariane133/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/nangate45/ariane136/BUILD.bazel b/flow/designs/nangate45/ariane136/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/nangate45/ariane136/BUILD.bazel +++ b/flow/designs/nangate45/ariane136/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/nangate45/black_parrot/BUILD.bazel b/flow/designs/nangate45/black_parrot/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/nangate45/black_parrot/BUILD.bazel +++ b/flow/designs/nangate45/black_parrot/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/nangate45/bp_be_top/BUILD.bazel b/flow/designs/nangate45/bp_be_top/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/nangate45/bp_be_top/BUILD.bazel +++ b/flow/designs/nangate45/bp_be_top/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/nangate45/bp_fe_top/BUILD.bazel b/flow/designs/nangate45/bp_fe_top/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/nangate45/bp_fe_top/BUILD.bazel +++ b/flow/designs/nangate45/bp_fe_top/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/nangate45/bp_multi_top/BUILD.bazel b/flow/designs/nangate45/bp_multi_top/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/nangate45/bp_multi_top/BUILD.bazel +++ b/flow/designs/nangate45/bp_multi_top/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/nangate45/bp_quad/BUILD.bazel b/flow/designs/nangate45/bp_quad/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/nangate45/bp_quad/BUILD.bazel +++ b/flow/designs/nangate45/bp_quad/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/nangate45/dynamic_node/BUILD.bazel b/flow/designs/nangate45/dynamic_node/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/nangate45/dynamic_node/BUILD.bazel +++ b/flow/designs/nangate45/dynamic_node/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/nangate45/gcd/BUILD.bazel b/flow/designs/nangate45/gcd/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/nangate45/gcd/BUILD.bazel +++ b/flow/designs/nangate45/gcd/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/nangate45/ibex/BUILD.bazel b/flow/designs/nangate45/ibex/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/nangate45/ibex/BUILD.bazel +++ b/flow/designs/nangate45/ibex/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/nangate45/jpeg/BUILD.bazel b/flow/designs/nangate45/jpeg/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/nangate45/jpeg/BUILD.bazel +++ b/flow/designs/nangate45/jpeg/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/nangate45/mempool_group/BUILD.bazel b/flow/designs/nangate45/mempool_group/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/nangate45/mempool_group/BUILD.bazel +++ b/flow/designs/nangate45/mempool_group/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/nangate45/swerv/BUILD.bazel b/flow/designs/nangate45/swerv/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/nangate45/swerv/BUILD.bazel +++ b/flow/designs/nangate45/swerv/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/nangate45/swerv_wrapper/BUILD.bazel b/flow/designs/nangate45/swerv_wrapper/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/nangate45/swerv_wrapper/BUILD.bazel +++ b/flow/designs/nangate45/swerv_wrapper/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/nangate45/tinyRocket/BUILD.bazel b/flow/designs/nangate45/tinyRocket/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/nangate45/tinyRocket/BUILD.bazel +++ b/flow/designs/nangate45/tinyRocket/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/sky130hd/aes/BUILD.bazel b/flow/designs/sky130hd/aes/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/sky130hd/aes/BUILD.bazel +++ b/flow/designs/sky130hd/aes/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/sky130hd/chameleon/BUILD.bazel b/flow/designs/sky130hd/chameleon/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/sky130hd/chameleon/BUILD.bazel +++ b/flow/designs/sky130hd/chameleon/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/sky130hd/chameleon/gds/BUILD.bazel b/flow/designs/sky130hd/chameleon/gds/BUILD.bazel index 64d9152242..ffe8da3a57 100644 --- a/flow/designs/sky130hd/chameleon/gds/BUILD.bazel +++ b/flow/designs/sky130hd/chameleon/gds/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.gds", "*.gds.gz"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "gds", - srcs = glob(["*.gds", "*.gds.gz"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("gds") diff --git a/flow/designs/sky130hd/chameleon/lef/BUILD.bazel b/flow/designs/sky130hd/chameleon/lef/BUILD.bazel index 4419ddd7a3..14238a10ec 100644 --- a/flow/designs/sky130hd/chameleon/lef/BUILD.bazel +++ b/flow/designs/sky130hd/chameleon/lef/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.lef"]), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "lef", - srcs = glob(["*.lef"]), - visibility = ["//visibility:public"], -) +files("lef") diff --git a/flow/designs/sky130hd/gcd/BUILD.bazel b/flow/designs/sky130hd/gcd/BUILD.bazel index 1054ff782a..fa2e42ab1a 100644 --- a/flow/designs/sky130hd/gcd/BUILD.bazel +++ b/flow/designs/sky130hd/gcd/BUILD.bazel @@ -1,6 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() diff --git a/flow/designs/sky130hd/ibex/BUILD.bazel b/flow/designs/sky130hd/ibex/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/sky130hd/ibex/BUILD.bazel +++ b/flow/designs/sky130hd/ibex/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/sky130hd/jpeg/BUILD.bazel b/flow/designs/sky130hd/jpeg/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/sky130hd/jpeg/BUILD.bazel +++ b/flow/designs/sky130hd/jpeg/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/sky130hd/microwatt/BUILD.bazel b/flow/designs/sky130hd/microwatt/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/sky130hd/microwatt/BUILD.bazel +++ b/flow/designs/sky130hd/microwatt/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/sky130hd/microwatt/gds/BUILD.bazel b/flow/designs/sky130hd/microwatt/gds/BUILD.bazel index 64d9152242..ffe8da3a57 100644 --- a/flow/designs/sky130hd/microwatt/gds/BUILD.bazel +++ b/flow/designs/sky130hd/microwatt/gds/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.gds", "*.gds.gz"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "gds", - srcs = glob(["*.gds", "*.gds.gz"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("gds") diff --git a/flow/designs/sky130hd/microwatt/lef/BUILD.bazel b/flow/designs/sky130hd/microwatt/lef/BUILD.bazel index 4419ddd7a3..14238a10ec 100644 --- a/flow/designs/sky130hd/microwatt/lef/BUILD.bazel +++ b/flow/designs/sky130hd/microwatt/lef/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.lef"]), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "lef", - srcs = glob(["*.lef"]), - visibility = ["//visibility:public"], -) +files("lef") diff --git a/flow/designs/sky130hd/microwatt/lib/BUILD.bazel b/flow/designs/sky130hd/microwatt/lib/BUILD.bazel index 5a1c76dc01..c477f56c5e 100644 --- a/flow/designs/sky130hd/microwatt/lib/BUILD.bazel +++ b/flow/designs/sky130hd/microwatt/lib/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.lib"]), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "lib", - srcs = glob(["*.lib"]), - visibility = ["//visibility:public"], -) +files("lib") diff --git a/flow/designs/sky130hd/riscv32i/BUILD.bazel b/flow/designs/sky130hd/riscv32i/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/sky130hd/riscv32i/BUILD.bazel +++ b/flow/designs/sky130hd/riscv32i/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/sky130hs/aes/BUILD.bazel b/flow/designs/sky130hs/aes/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/sky130hs/aes/BUILD.bazel +++ b/flow/designs/sky130hs/aes/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/sky130hs/gcd/BUILD.bazel b/flow/designs/sky130hs/gcd/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/sky130hs/gcd/BUILD.bazel +++ b/flow/designs/sky130hs/gcd/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/sky130hs/ibex/BUILD.bazel b/flow/designs/sky130hs/ibex/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/sky130hs/ibex/BUILD.bazel +++ b/flow/designs/sky130hs/ibex/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/sky130hs/jpeg/BUILD.bazel b/flow/designs/sky130hs/jpeg/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/sky130hs/jpeg/BUILD.bazel +++ b/flow/designs/sky130hs/jpeg/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/sky130hs/riscv32i/BUILD.bazel b/flow/designs/sky130hs/riscv32i/BUILD.bazel index 9ddf31b8b6..fa2e42ab1a 100644 --- a/flow/designs/sky130hs/riscv32i/BUILD.bazel +++ b/flow/designs/sky130hs/riscv32i/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +load("//flow/designs:design.bzl", "design") +design() diff --git a/flow/designs/src/aes/BUILD.bazel b/flow/designs/src/aes/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/aes/BUILD.bazel +++ b/flow/designs/src/aes/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/ariane/BUILD.bazel b/flow/designs/src/ariane/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/ariane/BUILD.bazel +++ b/flow/designs/src/ariane/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/ariane133/BUILD.bazel b/flow/designs/src/ariane133/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/ariane133/BUILD.bazel +++ b/flow/designs/src/ariane133/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/ariane136/BUILD.bazel b/flow/designs/src/ariane136/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/ariane136/BUILD.bazel +++ b/flow/designs/src/ariane136/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/black_parrot/BUILD.bazel b/flow/designs/src/black_parrot/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/black_parrot/BUILD.bazel +++ b/flow/designs/src/black_parrot/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/bp_be_top/BUILD.bazel b/flow/designs/src/bp_be_top/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/bp_be_top/BUILD.bazel +++ b/flow/designs/src/bp_be_top/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/bp_fe_top/BUILD.bazel b/flow/designs/src/bp_fe_top/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/bp_fe_top/BUILD.bazel +++ b/flow/designs/src/bp_fe_top/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/bp_multi_top/BUILD.bazel b/flow/designs/src/bp_multi_top/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/bp_multi_top/BUILD.bazel +++ b/flow/designs/src/bp_multi_top/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/bp_quad/BUILD.bazel b/flow/designs/src/bp_quad/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/bp_quad/BUILD.bazel +++ b/flow/designs/src/bp_quad/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/chameleon/AHB_sys_0/APB_sys_0/BUILD.bazel b/flow/designs/src/chameleon/AHB_sys_0/APB_sys_0/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/chameleon/AHB_sys_0/APB_sys_0/BUILD.bazel +++ b/flow/designs/src/chameleon/AHB_sys_0/APB_sys_0/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/chameleon/AHB_sys_0/BUILD.bazel b/flow/designs/src/chameleon/AHB_sys_0/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/chameleon/AHB_sys_0/BUILD.bazel +++ b/flow/designs/src/chameleon/AHB_sys_0/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/chameleon/BUILD.bazel b/flow/designs/src/chameleon/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/chameleon/BUILD.bazel +++ b/flow/designs/src/chameleon/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/chameleon/IPs/BUILD.bazel b/flow/designs/src/chameleon/IPs/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/chameleon/IPs/BUILD.bazel +++ b/flow/designs/src/chameleon/IPs/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/chameleon/IPs/apb2i2c/BUILD.bazel b/flow/designs/src/chameleon/IPs/apb2i2c/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/chameleon/IPs/apb2i2c/BUILD.bazel +++ b/flow/designs/src/chameleon/IPs/apb2i2c/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/chameleon/acc/BUILD.bazel b/flow/designs/src/chameleon/acc/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/chameleon/acc/BUILD.bazel +++ b/flow/designs/src/chameleon/acc/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/chameleon/ibex/BUILD.bazel b/flow/designs/src/chameleon/ibex/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/chameleon/ibex/BUILD.bazel +++ b/flow/designs/src/chameleon/ibex/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/chameleon/ibex/models/BUILD.bazel b/flow/designs/src/chameleon/ibex/models/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/chameleon/ibex/models/BUILD.bazel +++ b/flow/designs/src/chameleon/ibex/models/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/coyote/BUILD.bazel b/flow/designs/src/coyote/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/coyote/BUILD.bazel +++ b/flow/designs/src/coyote/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/BUILD.bazel b/flow/designs/src/cva6/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/BUILD.bazel +++ b/flow/designs/src/cva6/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/common/BUILD.bazel b/flow/designs/src/cva6/common/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/common/BUILD.bazel +++ b/flow/designs/src/cva6/common/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/common/local/BUILD.bazel b/flow/designs/src/cva6/common/local/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/common/local/BUILD.bazel +++ b/flow/designs/src/cva6/common/local/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/common/local/util/BUILD.bazel b/flow/designs/src/cva6/common/local/util/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/common/local/util/BUILD.bazel +++ b/flow/designs/src/cva6/common/local/util/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/BUILD.bazel b/flow/designs/src/cva6/core/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/BUILD.bazel +++ b/flow/designs/src/cva6/core/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cache_subsystem/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/BUILD.bazel +++ b/flow/designs/src/cva6/core/cache_subsystem/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/BUILD.bazel +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/BUILD.bazel +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/BUILD.bazel +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/BUILD.bazel +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/BUILD.bazel +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/BUILD.bazel +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/BUILD.bazel +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/BUILD.bazel +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cva6_mmu/BUILD.bazel b/flow/designs/src/cva6/core/cva6_mmu/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cva6_mmu/BUILD.bazel +++ b/flow/designs/src/cva6/core/cva6_mmu/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cvfpu/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cvfpu/BUILD.bazel +++ b/flow/designs/src/cva6/core/cvfpu/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cvfpu/src/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cvfpu/src/BUILD.bazel +++ b/flow/designs/src/cva6/core/cvfpu/src/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cvfpu/src/common_cells/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/common_cells/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cvfpu/src/common_cells/BUILD.bazel +++ b/flow/designs/src/cva6/core/cvfpu/src/common_cells/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/BUILD.bazel +++ b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/BUILD.bazel +++ b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cvxif_example/BUILD.bazel b/flow/designs/src/cva6/core/cvxif_example/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cvxif_example/BUILD.bazel +++ b/flow/designs/src/cva6/core/cvxif_example/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/cvxif_example/include/BUILD.bazel b/flow/designs/src/cva6/core/cvxif_example/include/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/cvxif_example/include/BUILD.bazel +++ b/flow/designs/src/cva6/core/cvxif_example/include/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/frontend/BUILD.bazel b/flow/designs/src/cva6/core/frontend/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/frontend/BUILD.bazel +++ b/flow/designs/src/cva6/core/frontend/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/pmp/BUILD.bazel b/flow/designs/src/cva6/core/pmp/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/pmp/BUILD.bazel +++ b/flow/designs/src/cva6/core/pmp/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/core/pmp/src/BUILD.bazel b/flow/designs/src/cva6/core/pmp/src/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/core/pmp/src/BUILD.bazel +++ b/flow/designs/src/cva6/core/pmp/src/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/vendor/BUILD.bazel b/flow/designs/src/cva6/vendor/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/vendor/BUILD.bazel +++ b/flow/designs/src/cva6/vendor/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/vendor/pulp-platform/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/vendor/pulp-platform/BUILD.bazel +++ b/flow/designs/src/cva6/vendor/pulp-platform/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/vendor/pulp-platform/axi/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/axi/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/vendor/pulp-platform/axi/BUILD.bazel +++ b/flow/designs/src/cva6/vendor/pulp-platform/axi/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/vendor/pulp-platform/axi/src/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/axi/src/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/vendor/pulp-platform/axi/src/BUILD.bazel +++ b/flow/designs/src/cva6/vendor/pulp-platform/axi/src/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/BUILD.bazel +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/BUILD.bazel +++ b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/BUILD.bazel +++ b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/BUILD.bazel +++ b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/BUILD.bazel index 7799a07b4f..115cf67d8f 100644 --- a/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/BUILD.bazel +++ b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/dynamic_node/BUILD.bazel b/flow/designs/src/dynamic_node/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/dynamic_node/BUILD.bazel +++ b/flow/designs/src/dynamic_node/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/ethmac/BUILD.bazel b/flow/designs/src/ethmac/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/ethmac/BUILD.bazel +++ b/flow/designs/src/ethmac/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/fifo/BUILD.bazel b/flow/designs/src/fifo/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/fifo/BUILD.bazel +++ b/flow/designs/src/fifo/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/gcd/BUILD.bazel b/flow/designs/src/gcd/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/gcd/BUILD.bazel +++ b/flow/designs/src/gcd/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/ibex_sv/BUILD.bazel b/flow/designs/src/ibex_sv/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/ibex_sv/BUILD.bazel +++ b/flow/designs/src/ibex_sv/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/BUILD.bazel b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/BUILD.bazel index 614a16235f..ce5093bdba 100644 --- a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/BUILD.bazel +++ b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "include", - srcs = glob(include = ["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("include") diff --git a/flow/designs/src/jpeg/BUILD.bazel b/flow/designs/src/jpeg/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/jpeg/BUILD.bazel +++ b/flow/designs/src/jpeg/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/mempool_group/BUILD.bazel b/flow/designs/src/mempool_group/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/mempool_group/BUILD.bazel +++ b/flow/designs/src/mempool_group/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/microwatt/BUILD.bazel b/flow/designs/src/microwatt/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/microwatt/BUILD.bazel +++ b/flow/designs/src/microwatt/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/mock-alu/BUILD.bazel b/flow/designs/src/mock-alu/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/mock-alu/BUILD.bazel +++ b/flow/designs/src/mock-alu/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/riscv32i/BUILD.bazel b/flow/designs/src/riscv32i/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/riscv32i/BUILD.bazel +++ b/flow/designs/src/riscv32i/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/spi/BUILD.bazel b/flow/designs/src/spi/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/spi/BUILD.bazel +++ b/flow/designs/src/spi/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/swerv/BUILD.bazel b/flow/designs/src/swerv/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/swerv/BUILD.bazel +++ b/flow/designs/src/swerv/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/tinyRocket/BUILD.bazel b/flow/designs/src/tinyRocket/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/tinyRocket/BUILD.bazel +++ b/flow/designs/src/tinyRocket/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/uart-no-param/BUILD.bazel b/flow/designs/src/uart-no-param/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/uart-no-param/BUILD.bazel +++ b/flow/designs/src/uart-no-param/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") diff --git a/flow/designs/src/uart/BUILD.bazel b/flow/designs/src/uart/BUILD.bazel index 8ccd944700..115cf67d8f 100644 --- a/flow/designs/src/uart/BUILD.bazel +++ b/flow/designs/src/uart/BUILD.bazel @@ -1,10 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") -filegroup( - name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +files("verilog") From e2d57116e460cad78f34a4f0506abd6f223542bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 21:48:42 +0200 Subject: [PATCH 08/28] build: drop design-specific entries from variables.yaml MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LIB_MODEL, SDC_FILE_EXTRA, MOCK_ALU_OPERATIONS, MOCK_ALU_WIDTH and MIN_CLK_ROUTING_LAYER are read by individual designs, not by ORFS itself. They belong in user_arguments on the orfs_flow() call site; landing them in the global variables.yaml conflated project knobs with ORFS knobs. Designs that reference these variables (asap7/gcd-ccs, asap7/mock-cpu, asap7/mock-alu, asap7/swerv_wrapper, asap7/riscv32i-mock-sram) now hit bazel-orfs's variable check at load time. Re-enabling them needs orfs_design() to forward user_arguments through to orfs_flow(). SYNTH_NUM_PARTITIONS stays — bazel-orfs auto-injects it for SYNTH_HIERARCHICAL designs and a downstream variables.yaml is the only hook that gates the validator today. Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 22 ------------------ flow/scripts/variables.json | 42 ---------------------------------- flow/scripts/variables.yaml | 45 ------------------------------------- 3 files changed, 109 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 2cb00d66d9..d2c229aadf 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -173,7 +173,6 @@ configuration file. | LEC_AUX_VERILOG_FILES| Additional Verilog files (e.g. blackbox stubs) to include in LEC equivalence checks. Appended to the generated Verilog netlist before running the formal equivalence check.| | | LEC_CHECK| Perform a formal equivalence check between before and after netlists. If this fails, report an issue to OpenROAD.| 0| | LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| | -| LIB_MODEL| Selects the standard cell library timing model. Set to CCS to use composite current source liberty files; default selects the NLDM (non-linear delay model) variant.| | | MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| | | MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| | | MACRO_PLACEMENT_TCL| Specifies the path of a TCL file on how to place macros manually. The user may choose to place just some of the macros in the design. The macro placer will handle the remaining unplaced macros.| | @@ -189,11 +188,8 @@ configuration file. | MAX_REPAIR_TIMING_ITER| Maximum number of iterations for repair setup and repair hold.| | | MAX_ROUTING_LAYER| The highest metal layer name to be used in routing.| | | MIN_BUF_CELL_AND_PORTS| Used to insert a buffer cell to pass through wires. Used in synthesis.| | -| MIN_CLK_ROUTING_LAYER| Lowest metal layer that clock tree synthesis may use for clock routing. Mirrors MIN_ROUTING_LAYER but applies to clock nets.| | | MIN_PLACE_STEP_COEF| Sets the minimum phi coefficient (pcof_min / µ_k Lower Bound) for global placement optimization. This parameter controls the step size lower bound in the RePlAce Nesterov optimization algorithm. Lower values may improve convergence but can increase runtime. Valid range: 0.95-1.05| 0.95| | MIN_ROUTING_LAYER| The lowest metal layer name to be used in routing.| | -| MOCK_ALU_OPERATIONS| Comma-separated list of ALU operations baked into the generated mock-alu RTL (e.g. ADD,SUB,AND). Consumed by the Chisel generator in src/mock-alu.| | -| MOCK_ALU_WIDTH| Datapath width in bits for the generated mock-alu RTL. Consumed by the Chisel generator in src/mock-alu.| | | NUM_CORES| Passed to `openroad -threads $(NUM_CORES)`, defaults to numbers of cores in system as determined by system specific code in Makefile, `nproc` is tried first. OpenROAD does not limit itself to this number of cores across OpenROAD running instances, which can lead to overprovisioning in contexts such as bazel-orfs where there could be many routing, or place jobs running at the same time.| | | OPENROAD_HIERARCHICAL| Feature toggle to enable to run OpenROAD in hierarchical mode, otherwise considered flat. Will eventually be the default and this option will be retired.| 0| | OR_K| Passed as -or_k to detailed routing.| | @@ -270,7 +266,6 @@ configuration file. | RUN_SCRIPT| Path to script to run from `make run`, python or tcl script detected by .py or .tcl extension.| | | SC_LEF| Path to technology standard cell LEF file.| | | SDC_FILE| The path to design constraint (SDC) file.| | -| SDC_FILE_EXTRA| Path to an additional Tcl file sourced from constraint.sdc and from place_pins I/O scripts. Used by designs that share helper Tcl between SDC and pin placement (e.g. mock-cpu).| | | SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | | SEAL_GDS| Seal macro to place around the design.| | | SETUP_MOVE_SEQUENCE| Passed as -sequence to repair_timing. This should be a string of move keywords separated by commas.| | @@ -348,14 +343,10 @@ configuration file. - [DFF_LIB_FILE](#DFF_LIB_FILE) - [DFF_MAP_FILE](#DFF_MAP_FILE) - [LATCH_MAP_FILE](#LATCH_MAP_FILE) -- [LIB_MODEL](#LIB_MODEL) - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS) -- [MOCK_ALU_OPERATIONS](#MOCK_ALU_OPERATIONS) -- [MOCK_ALU_WIDTH](#MOCK_ALU_WIDTH) - [POST_SYNTH_TCL](#POST_SYNTH_TCL) - [PRE_SYNTH_TCL](#PRE_SYNTH_TCL) - [SDC_FILE](#SDC_FILE) -- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SDC_GUT](#SDC_GUT) - [SLANG_PLUGIN_PATH](#SLANG_PLUGIN_PATH) - [SYNTH_ARGS](#SYNTH_ARGS) @@ -405,7 +396,6 @@ configuration file. - [FOOTPRINT_TCL](#FOOTPRINT_TCL) - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) - [IO_CONSTRAINTS](#IO_CONSTRAINTS) -- [LIB_MODEL](#LIB_MODEL) - [MACRO_BLOCKAGE_HALO](#MACRO_BLOCKAGE_HALO) - [MACRO_PLACEMENT_TCL](#MACRO_PLACEMENT_TCL) - [MACRO_PLACE_HALO](#MACRO_PLACE_HALO) @@ -448,7 +438,6 @@ configuration file. - [RTLMP_OUTLINE_WT](#RTLMP_OUTLINE_WT) - [RTLMP_RPT_DIR](#RTLMP_RPT_DIR) - [RTLMP_WIRELENGTH_WT](#RTLMP_WIRELENGTH_WT) -- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SETUP_MOVE_SEQUENCE](#SETUP_MOVE_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_BUFFER_REMOVAL](#SKIP_BUFFER_REMOVAL) @@ -483,7 +472,6 @@ configuration file. - [GPL_TIMING_DRIVEN](#GPL_TIMING_DRIVEN) - [IO_PLACER_H](#IO_PLACER_H) - [IO_PLACER_V](#IO_PLACER_V) -- [LIB_MODEL](#LIB_MODEL) - [MATCH_CELL_FOOTPRINT](#MATCH_CELL_FOOTPRINT) - [MAX_PLACE_STEP_COEF](#MAX_PLACE_STEP_COEF) - [MAX_REPAIR_TIMING_ITER](#MAX_REPAIR_TIMING_ITER) @@ -506,7 +494,6 @@ configuration file. - [PRE_REPAIR_TIMING_POST_PLACE_TCL](#PRE_REPAIR_TIMING_POST_PLACE_TCL) - [PRE_RESIZE_TCL](#PRE_RESIZE_TCL) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) -- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) - [TNS_END_PERCENT](#TNS_END_PERCENT) @@ -525,14 +512,11 @@ configuration file. - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) - [LEC_AUX_VERILOG_FILES](#LEC_AUX_VERILOG_FILES) - [LEC_CHECK](#LEC_CHECK) -- [LIB_MODEL](#LIB_MODEL) - [MATCH_CELL_FOOTPRINT](#MATCH_CELL_FOOTPRINT) - [MAX_REPAIR_TIMING_ITER](#MAX_REPAIR_TIMING_ITER) -- [MIN_CLK_ROUTING_LAYER](#MIN_CLK_ROUTING_LAYER) - [POST_CTS_TCL](#POST_CTS_TCL) - [PRE_CTS_TCL](#PRE_CTS_TCL) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) -- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SETUP_MOVE_SEQUENCE](#SETUP_MOVE_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_BUFFER_REMOVAL](#SKIP_BUFFER_REMOVAL) @@ -552,7 +536,6 @@ configuration file. - [ENABLE_RESISTANCE_AWARE](#ENABLE_RESISTANCE_AWARE) - [GLOBAL_ROUTE_ARGS](#GLOBAL_ROUTE_ARGS) - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) -- [LIB_MODEL](#LIB_MODEL) - [MAX_REPAIR_ANTENNAS_ITER_GRT](#MAX_REPAIR_ANTENNAS_ITER_GRT) - [MAX_REPAIR_TIMING_ITER](#MAX_REPAIR_TIMING_ITER) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) @@ -561,7 +544,6 @@ configuration file. - [PRE_GLOBAL_ROUTE_TCL](#PRE_GLOBAL_ROUTE_TCL) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) -- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SETUP_MOVE_SEQUENCE](#SETUP_MOVE_SEQUENCE) - [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN) - [SKIP_ANTENNA_REPAIR](#SKIP_ANTENNA_REPAIR) @@ -584,7 +566,6 @@ configuration file. - [DETAILED_ROUTE_END_ITERATION](#DETAILED_ROUTE_END_ITERATION) - [DISABLE_VIA_GEN](#DISABLE_VIA_GEN) - [FILL_CELLS](#FILL_CELLS) -- [LIB_MODEL](#LIB_MODEL) - [MATCH_CELL_FOOTPRINT](#MATCH_CELL_FOOTPRINT) - [MAX_REPAIR_ANTENNAS_ITER_DRT](#MAX_REPAIR_ANTENNAS_ITER_DRT) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) @@ -597,7 +578,6 @@ configuration file. - [PRE_FILLCELL_TCL](#PRE_FILLCELL_TCL) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) -- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SKIP_ANTENNA_REPAIR_POST_DRT](#SKIP_ANTENNA_REPAIR_POST_DRT) - [SKIP_DETAILED_ROUTE](#SKIP_DETAILED_ROUTE) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) @@ -610,7 +590,6 @@ configuration file. - [CDL_FILE](#CDL_FILE) - [GDS_ALLOW_EMPTY](#GDS_ALLOW_EMPTY) - [GND_NETS_VOLTAGES](#GND_NETS_VOLTAGES) -- [LIB_MODEL](#LIB_MODEL) - [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER) - [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER) - [POST_DENSITY_FILL_TCL](#POST_DENSITY_FILL_TCL) @@ -620,7 +599,6 @@ configuration file. - [PWR_NETS_VOLTAGES](#PWR_NETS_VOLTAGES) - [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW) - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT) -- [SDC_FILE_EXTRA](#SDC_FILE_EXTRA) - [SKIP_DETAILED_ROUTE](#SKIP_DETAILED_ROUTE) - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS) diff --git a/flow/scripts/variables.json b/flow/scripts/variables.json index 392cd30d25..3e3d49755e 100644 --- a/flow/scripts/variables.json +++ b/flow/scripts/variables.json @@ -483,18 +483,6 @@ "LIB_FILES": { "description": "A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.\n" }, - "LIB_MODEL": { - "description": "Selects the standard cell library timing model. Set to CCS to use composite current source liberty files; default selects the NLDM (non-linear delay model) variant.\n", - "stages": [ - "synth", - "floorplan", - "place", - "cts", - "grt", - "route", - "final" - ] - }, "MACRO_BLOCKAGE_HALO": { "description": "Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.\n", "stages": [ @@ -598,12 +586,6 @@ "synth" ] }, - "MIN_CLK_ROUTING_LAYER": { - "description": "Lowest metal layer that clock tree synthesis may use for clock routing. Mirrors MIN_ROUTING_LAYER but applies to clock nets.\n", - "stages": [ - "cts" - ] - }, "MIN_PLACE_STEP_COEF": { "default": 0.95, "description": "Sets the minimum phi coefficient (pcof_min / \u00b5_k Lower Bound) for global placement optimization. This parameter controls the step size lower bound in the RePlAce Nesterov optimization algorithm. Lower values may improve convergence but can increase runtime. Valid range: 0.95-1.05\n", @@ -623,18 +605,6 @@ "final" ] }, - "MOCK_ALU_OPERATIONS": { - "description": "Comma-separated list of ALU operations baked into the generated mock-alu RTL (e.g. ADD,SUB,AND). Consumed by the Chisel generator in src/mock-alu.\n", - "stages": [ - "synth" - ] - }, - "MOCK_ALU_WIDTH": { - "description": "Datapath width in bits for the generated mock-alu RTL. Consumed by the Chisel generator in src/mock-alu.\n", - "stages": [ - "synth" - ] - }, "NUM_CORES": { "description": "Passed to `openroad -threads $(NUM_CORES)`, defaults to numbers of cores in system as determined by system specific code in Makefile, `nproc` is tried first. OpenROAD does not limit itself to this number of cores across OpenROAD running instances, which can lead to overprovisioning in contexts such as bazel-orfs where there could be many routing, or place jobs running at the same time.\n", "stages": [ @@ -1095,18 +1065,6 @@ "synth" ] }, - "SDC_FILE_EXTRA": { - "description": "Path to an additional Tcl file sourced from constraint.sdc and from place_pins I/O scripts. Used by designs that share helper Tcl between SDC and pin placement (e.g. mock-cpu).\n", - "stages": [ - "synth", - "floorplan", - "place", - "cts", - "grt", - "route", - "final" - ] - }, "SDC_GUT": { "description": "Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.\n", "stages": [ diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 4f646c3299..94f1e4fe78 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -1585,38 +1585,6 @@ CDL_FILE: for generating Circuit Description Language output. stages: - final -LIB_MODEL: - description: > - Selects the standard cell library timing model. Set to CCS to use - composite current source liberty files; default selects the NLDM - (non-linear delay model) variant. - stages: - - synth - - floorplan - - place - - cts - - grt - - route - - final -MIN_CLK_ROUTING_LAYER: - description: > - Lowest metal layer that clock tree synthesis may use for clock - routing. Mirrors MIN_ROUTING_LAYER but applies to clock nets. - stages: - - cts -SDC_FILE_EXTRA: - description: > - Path to an additional Tcl file sourced from constraint.sdc and from - place_pins I/O scripts. Used by designs that share helper Tcl - between SDC and pin placement (e.g. mock-cpu). - stages: - - synth - - floorplan - - place - - cts - - grt - - route - - final SYNTH_NUM_PARTITIONS: description: > Total number of partitions used by the parallel synthesis flow. @@ -1624,16 +1592,3 @@ SYNTH_NUM_PARTITIONS: typically set by users. stages: - synth -MOCK_ALU_OPERATIONS: - description: > - Comma-separated list of ALU operations baked into the generated - mock-alu RTL (e.g. ADD,SUB,AND). Consumed by the Chisel generator - in src/mock-alu. - stages: - - synth -MOCK_ALU_WIDTH: - description: > - Datapath width in bits for the generated mock-alu RTL. Consumed by - the Chisel generator in src/mock-alu. - stages: - - synth From 1236e7dc2c7ab9c3db19b27ef2b51bd120d150a4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 21:58:10 +0200 Subject: [PATCH 09/28] build: drop unused entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - variables.yaml: drop SYNTH_NUM_PARTITIONS. ORFS doesn't read it; only bazel-orfs's parallel-synth wrapper does, and that's a bazel-orfs internal concern. - .bazelrc: drop --experimental_isolated_extension_usages. We don't use isolate=True on any use_extension call. - flow/designs/asap7/minimal/BUILD.bazel: drop the orfs_design loads the file no longer needs since orfs_design isn't called here. - bazel-orfs.md: drop the "Local bazel-orfs" section and update the add-a-design snippets to use the new design.bzl macros. Signed-off-by: Øyvind Harboe --- .bazelrc | 1 - bazel-orfs.md | 18 +++++------------- docs/user/FlowVariables.md | 2 -- flow/designs/asap7/minimal/BUILD.bazel | 6 +----- flow/scripts/variables.json | 6 ------ flow/scripts/variables.yaml | 7 ------- 6 files changed, 6 insertions(+), 34 deletions(-) diff --git a/.bazelrc b/.bazelrc index 2a3ecca931..826c4e5375 100644 --- a/.bazelrc +++ b/.bazelrc @@ -1,4 +1,3 @@ build --incompatible_strict_action_env -common --experimental_isolated_extension_usages build --cxxopt "-std=c++20" --host_cxxopt "-std=c++20" try-import %workspace%/user.bazelrc diff --git a/bazel-orfs.md b/bazel-orfs.md index 1e73a5f376..9c4f2ff678 100644 --- a/bazel-orfs.md +++ b/bazel-orfs.md @@ -35,30 +35,22 @@ bazelisk query //flow/designs/asap7/...:* ```starlark # flow/designs///BUILD.bazel -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("//flow/designs:design.bzl", "design") -exports_files(glob(["*"])) - -orfs_design(designs = DESIGNS) +design() ``` If `flow/designs/src//BUILD.bazel` is missing, add: ```starlark -exports_files(glob(["*.v", "*.sv"], allow_empty = True), visibility = ["//visibility:public"]) -filegroup(name = "verilog", srcs = glob(["*.v", "*.sv"], allow_empty = True), visibility = ["//visibility:public"]) +load("//flow/designs:design.bzl", "files") + +files("verilog") ``` A design counts as CI-tested iff `rules-base.json` exists; without it the generated targets get `tags = ["manual"]`. -## Local bazel-orfs - -Replace the `git_override` for `bazel-orfs` and `bazel-orfs-verilog` in -`MODULE.bazel` with `local_path_override` pointing at the checkout -(and `…/verilog` for the latter). - ## Parallelism Each OpenROAD invocation takes `-threads `. A wildcard diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index d2c229aadf..80d3073bc5 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -303,7 +303,6 @@ configuration file. | SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0| | SYNTH_MOCK_LARGE_MEMORIES| Reduce Yosys inferred memories larger than SYNTH_MEMORY_MAX_BITS to 1 row. Yosys will generally infer memories from behavioral Verilog code, whether the memories are in standalone modules or instantiated within some larger module. fakeram and empty Verilog memories(blackboxes) of memories will not be inferred memories by Yosys and are therefore not affected by this variable. This is useful and convenient to separate the concern of instantiating and placing memories from investigating other issues with a design, though it comes at the expense of the increased accuracy that using realistic fakemem would provide. Memories with a single 1 row will of course have unrealistically good timing and area characteristics, but timing will still correctly terminate in a register. Large port memories, typically register files, will still have the retain a lot of the port logic that can be useful to investigate issues. This can be especially useful during development of designs where the behavioral model comes first and suitable memories are matched up when the design RTL is stable. A typical use case would be Chisel which will generate a behavioral model for a memories with the required clocks, ports, etc. in addition to a computer readable file with the specification of the memories that is used to [automatically](https://chipyard.readthedocs.io/en/stable/Tools/Barstools.html/) match up suitable memory macros later in the flow. During an architectural screening study, a large range of memory configurations can be investigated quickly with this option, without getting bogged down in the concern of how to realize the memories in silicon for emphemral RTL configurations that exist only long enough to run through the ORFS flow to create a table of some characteristics of a design configuration.| 0| | SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | -| SYNTH_NUM_PARTITIONS| Total number of partitions used by the parallel synthesis flow. Set automatically by bazel-orfs based on SYNTH_KEEP_MODULES; not typically set by users.| | | SYNTH_OPERATIONS_ARGS| Extra arguments appended to the Yosys synth command operations list. When set, replaces the default Kogge-Stone adder extra-map.| | | SYNTH_OPT_HIER| Optimize constants across hierarchical boundaries.| | | SYNTH_REPEATABLE_BUILD| License to prune anything that makes builds less repeatable, typically used with Bazel to ensure that builds are bit-for-bit identical so that caching works optimally. Removes debug information that encodes paths, timestamps, etc.| 0| @@ -364,7 +363,6 @@ configuration file. - [SYNTH_MINIMUM_KEEP_SIZE](#SYNTH_MINIMUM_KEEP_SIZE) - [SYNTH_MOCK_LARGE_MEMORIES](#SYNTH_MOCK_LARGE_MEMORIES) - [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES) -- [SYNTH_NUM_PARTITIONS](#SYNTH_NUM_PARTITIONS) - [SYNTH_OPERATIONS_ARGS](#SYNTH_OPERATIONS_ARGS) - [SYNTH_OPT_HIER](#SYNTH_OPT_HIER) - [SYNTH_REPEATABLE_BUILD](#SYNTH_REPEATABLE_BUILD) diff --git a/flow/designs/asap7/minimal/BUILD.bazel b/flow/designs/asap7/minimal/BUILD.bazel index 3835f0fd1c..75ee41fcd8 100644 --- a/flow/designs/asap7/minimal/BUILD.bazel +++ b/flow/designs/asap7/minimal/BUILD.bazel @@ -1,7 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") - exports_files(glob(["*"])) -# TODO(bazel-orfs): orfs_design(designs = DESIGNS) -# Blocked: no VERILOG_FILES in config.mk (test-only design with empty SDC). +# Skipped: minimal has no VERILOG_FILES in config.mk (empty SDC test design). diff --git a/flow/scripts/variables.json b/flow/scripts/variables.json index 3e3d49755e..0c8e56ad77 100644 --- a/flow/scripts/variables.json +++ b/flow/scripts/variables.json @@ -1320,12 +1320,6 @@ "synth" ] }, - "SYNTH_NUM_PARTITIONS": { - "description": "Total number of partitions used by the parallel synthesis flow. Set automatically by bazel-orfs based on SYNTH_KEEP_MODULES; not typically set by users.\n", - "stages": [ - "synth" - ] - }, "SYNTH_OPERATIONS_ARGS": { "description": "Extra arguments appended to the Yosys synth command operations list. When set, replaces the default Kogge-Stone adder extra-map.\n", "stages": [ diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 94f1e4fe78..c8cbfb7898 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -1585,10 +1585,3 @@ CDL_FILE: for generating Circuit Description Language output. stages: - final -SYNTH_NUM_PARTITIONS: - description: > - Total number of partitions used by the parallel synthesis flow. - Set automatically by bazel-orfs based on SYNTH_KEEP_MODULES; not - typically set by users. - stages: - - synth From bdd7af0910b64a942761984451aaa8801c99b6c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 22:05:05 +0200 Subject: [PATCH 10/28] tmp: ignore MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Øyvind Harboe --- .bazelignore | 1 + .gitignore | 1 + 2 files changed, 2 insertions(+) diff --git a/.bazelignore b/.bazelignore index 7bfdcf03d8..819d9bf3eb 100644 --- a/.bazelignore +++ b/.bazelignore @@ -6,3 +6,4 @@ jenkins/ docs/ +tmp diff --git a/.gitignore b/.gitignore index 37ebf3fa79..bf806b0ee6 100644 --- a/.gitignore +++ b/.gitignore @@ -105,3 +105,4 @@ bazel-testlogs # python venv venv/ +tmp/ From 4730b294ff3b7604e949d724f4de899f7d31632b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 22:15:46 +0200 Subject: [PATCH 11/28] build: revert unintended rules-base.json changes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These three designs fail to load at all under bazel (missing :macros.v / :adjusted-gf180mcu_*.lef targets and SYNTH_NUM_PARTITIONS validation), so the regenerated thresholds had no effect anyway. The branch picked them up via the soft-merge; restore master's values. Signed-off-by: Øyvind Harboe --- flow/designs/gf180/aes-hybrid/rules-base.json | 24 +++++----- .../nangate45/ariane136/rules-base.json | 46 ++++++++++--------- .../nangate45/bp_be_top/rules-base.json | 34 ++++++++------ 3 files changed, 56 insertions(+), 48 deletions(-) diff --git a/flow/designs/gf180/aes-hybrid/rules-base.json b/flow/designs/gf180/aes-hybrid/rules-base.json index b84e9c6447..42ece06169 100644 --- a/flow/designs/gf180/aes-hybrid/rules-base.json +++ b/flow/designs/gf180/aes-hybrid/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 634000.0, + "value": 489779.41376, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 834351, + "value": 650139, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 24157, + "value": 21903, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 2101, + "value": 1831, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 2101, + "value": 1831, "compare": "<=" }, "cts__timing__setup__ws": { - "value": -1.02, + "value": -1.14, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -113.0, + "value": -137.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -143.0, + "value": -154.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 1869441, + "value": 1501193, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -80,11 +80,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -1.26, + "value": -1.28, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -140.0, + "value": -148.0, "compare": ">=" }, "finish__timing__hold__ws": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 895937, + "value": 752796, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/ariane136/rules-base.json b/flow/designs/nangate45/ariane136/rules-base.json index 5657ee419c..e48b97d4ae 100644 --- a/flow/designs/nangate45/ariane136/rules-base.json +++ b/flow/designs/nangate45/ariane136/rules-base.json @@ -1,14 +1,18 @@ { + "synth__design__instance__area__stdcell": { + "value": 845000.0, + "compare": "<=" + }, "constraints__clocks__count": { - "value": 0, + "value": 1, "compare": "==" }, "placeopt__design__instance__area": { - "value": 853835, + "value": 847520, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 208889, + "value": 196993, "compare": "<=" }, "detailedplace__design__violations": { @@ -16,51 +20,51 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 18164, + "value": 17130, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 18164, + "value": 17130, "compare": "<=" }, "cts__timing__setup__ws": { - "value": 0.0, + "value": -0.3, "compare": ">=" }, "cts__timing__setup__tns": { - "value": 0.0, + "value": -1.2, "compare": ">=" }, "cts__timing__hold__ws": { - "value": 0.0, + "value": -0.678, "compare": ">=" }, "cts__timing__hold__tns": { - "value": 0.0, + "value": -8.05, "compare": ">=" }, "globalroute__antenna_diodes_count": { - "value": 196, + "value": 200, "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": 0.0, + "value": -0.3, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": 0.0, + "value": -1.2, "compare": ">=" }, "globalroute__timing__hold__ws": { - "value": 0.0, + "value": -0.3, "compare": ">=" }, "globalroute__timing__hold__tns": { - "value": 0.0, + "value": -1.2, "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 7740320, + "value": 8033923, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -72,27 +76,27 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 196, + "value": 201, "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -0.3, "compare": ">=" }, "finish__timing__setup__tns": { - "value": 0.0, + "value": -1.2, "compare": ">=" }, "finish__timing__hold__ws": { - "value": 0.0, + "value": -0.3, "compare": ">=" }, "finish__timing__hold__tns": { - "value": 0.0, + "value": -1.2, "compare": ">=" }, "finish__design__instance__area": { - "value": 853954, + "value": 858672, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/nangate45/bp_be_top/rules-base.json b/flow/designs/nangate45/bp_be_top/rules-base.json index 876f707c29..2140525de9 100644 --- a/flow/designs/nangate45/bp_be_top/rules-base.json +++ b/flow/designs/nangate45/bp_be_top/rules-base.json @@ -1,14 +1,18 @@ { + "synth__design__instance__area__stdcell": { + "value": 268204.56, + "compare": "<=" + }, "constraints__clocks__count": { - "value": 0, + "value": 1, "compare": "==" }, "placeopt__design__instance__area": { - "value": 310391, + "value": 273548, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 84218, + "value": 62588, "compare": "<=" }, "detailedplace__design__violations": { @@ -16,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 7323, + "value": 5442, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 7323, + "value": 5442, "compare": "<=" }, "cts__timing__setup__ws": { - "value": 0.0, + "value": -0.411, "compare": ">=" }, "cts__timing__setup__tns": { - "value": 0.0, + "value": -24.3, "compare": ">=" }, "cts__timing__hold__ws": { @@ -40,15 +44,15 @@ "compare": ">=" }, "globalroute__antenna_diodes_count": { - "value": 100, + "value": 0, "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": 0.0, + "value": -0.427, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": 0.0, + "value": -29.9, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -60,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 2732383, + "value": 2504235, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -72,15 +76,15 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 100, + "value": 5, "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -0.418, "compare": ">=" }, "finish__timing__setup__tns": { - "value": 0.0, + "value": -28.5, "compare": ">=" }, "finish__timing__hold__ws": { @@ -92,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 310405, + "value": 275387, "compare": "<=" } } \ No newline at end of file From 04b31a6cfd2d5b91417375b8fb52cf3dfb74ca61 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 22:23:03 +0200 Subject: [PATCH 12/28] build: patch bazel-orfs to register injected SYNTH_NUM_PARTITIONS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit bazel-orfs auto-injects SYNTH_NUM_PARTITIONS into the orfs_flow() arguments dict when SYNTH_HIERARCHICAL=1, but its check_variables() walks every key in arguments and fails on anything not in the downstream variables.yaml -- so the validator was complaining about a variable bazel-orfs put there itself. ORFS doesn't read it, so adding it to ORFS variables.yaml is wrong. Patch private/stages.bzl to populate BAZEL_VARIABLE_TO_STAGES with SYNTH_NUM_PARTITIONS and merge BAZEL_STAGE_TO_VARIABLES into ALL_STAGE_TO_VARIABLES (it was previously declared as an empty dict and never used). To be upstreamed. Signed-off-by: Øyvind Harboe --- MODULE.bazel | 4 ++ ...ter-bazel-injected-vars-in-validator.patch | 48 +++++++++++++++++++ bazel/bazel-orfs-patches/BUILD.bazel | 1 + 3 files changed, 53 insertions(+) create mode 100644 bazel/bazel-orfs-patches/0001-stages-register-bazel-injected-vars-in-validator.patch create mode 100644 bazel/bazel-orfs-patches/BUILD.bazel diff --git a/MODULE.bazel b/MODULE.bazel index 97b040762f..28a91dd963 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -35,6 +35,10 @@ BAZEL_ORFS_REMOTE = "https://github.com/The-OpenROAD-Project/bazel-orfs.git" git_override( module_name = "bazel-orfs", commit = BAZEL_ORFS_COMMIT, + patch_strip = 1, + patches = [ + "//bazel/bazel-orfs-patches:0001-stages-register-bazel-injected-vars-in-validator.patch", + ], remote = BAZEL_ORFS_REMOTE, ) diff --git a/bazel/bazel-orfs-patches/0001-stages-register-bazel-injected-vars-in-validator.patch b/bazel/bazel-orfs-patches/0001-stages-register-bazel-injected-vars-in-validator.patch new file mode 100644 index 0000000000..358eaa343a --- /dev/null +++ b/bazel/bazel-orfs-patches/0001-stages-register-bazel-injected-vars-in-validator.patch @@ -0,0 +1,48 @@ +diff --git a/private/stages.bzl b/private/stages.bzl +index 8c1391a..28e8afa 100644 +--- a/private/stages.bzl ++++ b/private/stages.bzl +@@ -6,9 +6,31 @@ load("//private:utils.bzl", "flatten", "set", "union") + # A stage argument is used in one or more stages. This is metainformation + # about the ORFS code that there is no known nice way for ORFS to + # provide. +-BAZEL_VARIABLE_TO_STAGES = {} ++# ++# Variables auto-injected by bazel-orfs (not present in ORFS variables.yaml) ++# are registered here so that check_variables() does not flag them as ++# unknown when downstream callers see them in arguments. ++BAZEL_VARIABLE_TO_STAGES = { ++ # Set in orfs_design.bzl when SYNTH_HIERARCHICAL=1. ++ "SYNTH_NUM_PARTITIONS": ["synth"], ++} + +-BAZEL_STAGE_TO_VARIABLES = {} ++BAZEL_STAGE_TO_VARIABLES = { ++ stage: [v for v, stages in BAZEL_VARIABLE_TO_STAGES.items() if stage in stages] ++ for stage in [ ++ "synth", ++ "floorplan", ++ "place", ++ "cts", ++ "grt", ++ "route", ++ "final", ++ "generate_abstract", ++ "generate_metadata", ++ "test", ++ "update_rules", ++ ] ++} + + ALL_STAGES = [ + "synth", +@@ -135,7 +157,8 @@ ORFS_STAGE_TO_VARIABLES = { + } + + ALL_STAGE_TO_VARIABLES = { +- stage: ORFS_STAGE_TO_VARIABLES.get(stage, []) ++ stage: ORFS_STAGE_TO_VARIABLES.get(stage, []) + ++ BAZEL_STAGE_TO_VARIABLES.get(stage, []) + for stage in ALL_STAGES + } + diff --git a/bazel/bazel-orfs-patches/BUILD.bazel b/bazel/bazel-orfs-patches/BUILD.bazel new file mode 100644 index 0000000000..d518110449 --- /dev/null +++ b/bazel/bazel-orfs-patches/BUILD.bazel @@ -0,0 +1 @@ +exports_files(glob(["*.patch"])) From 282ca3f809f52d99ec2e04b68059924e5a2fa3a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 22:36:47 +0200 Subject: [PATCH 13/28] nangate45: drop dead PLACE_DENSITY_MAX_POST_HOLD from bp_fe_top MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The variable is set in this design's config.mk but read nowhere in ORFS or OpenROAD. With strict variable validation in bazel-orfs, it was the last thing keeping bp_fe_top from loading. Signed-off-by: Øyvind Harboe --- flow/designs/nangate45/bp_fe_top/config.mk | 1 - 1 file changed, 1 deletion(-) diff --git a/flow/designs/nangate45/bp_fe_top/config.mk b/flow/designs/nangate45/bp_fe_top/config.mk index 633035aa22..b63012a4ba 100644 --- a/flow/designs/nangate45/bp_fe_top/config.mk +++ b/flow/designs/nangate45/bp_fe_top/config.mk @@ -25,7 +25,6 @@ export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io.tcl export MACRO_PLACE_HALO = 10 10 export PLACE_DENSITY_LB_ADDON = 0.11 -export PLACE_DENSITY_MAX_POST_HOLD = 0.13 export TNS_END_PERCENT = 100 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl From 732c69ae1255452164c48ca0976a063a7e2d34fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 4 May 2026 23:02:12 +0200 Subject: [PATCH 14/28] build: patch bazel-orfs synth_partition SYNTH_SKIP_KEEP truthy check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ORFS variables.yaml defaults SYNTH_SKIP_KEEP to "0" and emits 'export SYNTH_SKIP_KEEP?=0' via defaults.py. bazel-orfs's synth_partition.sh tested the env var with [ -n "$SYNTH_SKIP_KEEP" ], which is true for any non-empty string -- so "0" took the skip-keep branch and grep'd for 1_1_yosys_canonicalize.rtlil that wasn't in the partition action's sandbox. Switch the test to an explicit "1" comparison. Verified with bazelisk build //flow/designs/nangate45/bp_be_top:bp_be_top_synth, which now completes (was failing on the spurious grep). Signed-off-by: Øyvind Harboe --- MODULE.bazel | 1 + ...tion-fix-SYNTH_SKIP_KEEP-truthy-check.patch | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 bazel/bazel-orfs-patches/0002-synth_partition-fix-SYNTH_SKIP_KEEP-truthy-check.patch diff --git a/MODULE.bazel b/MODULE.bazel index 28a91dd963..e0b98e49a2 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -38,6 +38,7 @@ git_override( patch_strip = 1, patches = [ "//bazel/bazel-orfs-patches:0001-stages-register-bazel-injected-vars-in-validator.patch", + "//bazel/bazel-orfs-patches:0002-synth_partition-fix-SYNTH_SKIP_KEEP-truthy-check.patch", ], remote = BAZEL_ORFS_REMOTE, ) diff --git a/bazel/bazel-orfs-patches/0002-synth_partition-fix-SYNTH_SKIP_KEEP-truthy-check.patch b/bazel/bazel-orfs-patches/0002-synth_partition-fix-SYNTH_SKIP_KEEP-truthy-check.patch new file mode 100644 index 0000000000..66516e89ef --- /dev/null +++ b/bazel/bazel-orfs-patches/0002-synth_partition-fix-SYNTH_SKIP_KEEP-truthy-check.patch @@ -0,0 +1,18 @@ +diff --git a/synth_partition.sh b/synth_partition.sh +index bf3deb5..5fa420b 100755 +--- a/synth_partition.sh ++++ b/synth_partition.sh +@@ -21,9 +21,11 @@ OUTPUT="$RESULTS_DIR/partition_${PARTITION_ID}.v" + # JSON format: {"modules": ["mod1", "mod2", ...]} + ALL_MODULES=$(sed 's/.*\[//;s/\].*//;s/"//g;s/,/\n/g;s/ //g' "$KEPT_JSON") + +-# When SYNTH_SKIP_KEEP is set, the keep-hierarchy discovery was skipped. ++# When SYNTH_SKIP_KEEP=1, the keep-hierarchy discovery was skipped. + # Partitions read from canonical RTLIL and run full synthesis (coarse+fine). +-if [ -n "${SYNTH_SKIP_KEEP:-}" ]; then ++# ORFS variables.yaml defaults SYNTH_SKIP_KEEP to "0", so test for "1" ++# explicitly rather than -n (which is true for any non-empty string). ++if [ "${SYNTH_SKIP_KEEP:-0}" = "1" ]; then + CHECKPOINT="$RESULTS_DIR/1_1_yosys_canonicalize.rtlil" + # Validate that every SYNTH_KEEP_MODULES entry exists in the canonical RTLIL + RTLIL_MODULES_FILE=$(mktemp) From 5f03d436f773d33da6bfd3d6bcfb9301aa858eed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 5 May 2026 05:20:03 +0200 Subject: [PATCH 15/28] build: patch bazel-orfs synth_partition kept_modules.json parse MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The sed-based parser used greedy '.*\\[' / '\\].*' regexes. Slang elaborates parameterized instances into names that contain '[' and ']' (e.g. 'tcdm_adapter\$mempool_group.gen_tiles[0].i_tile.gen_banks[0]'), so the greedy match strips most of the JSON and leaves a single nonsense module name like '0'. nangate45/mempool_group hit this and its partition action would print 'synthesizing 1 modules: 0' before failing with 'Module \`0' not found'. Module names cannot contain '"', so 'grep -oE "\\"[^\"]+\\""' followed by 'tail -n +2' (skip the "modules" key) is a safe parse without greedy backtracking. Verified with 'bazelisk build //flow/designs/nangate45/mempool_group:mempool_group_synth', which now completes. Signed-off-by: Øyvind Harboe --- MODULE.bazel | 1 + ...kept_modules-json-without-greedy-sed.patch | 20 +++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 bazel/bazel-orfs-patches/0003-synth_partition-parse-kept_modules-json-without-greedy-sed.patch diff --git a/MODULE.bazel b/MODULE.bazel index e0b98e49a2..3645ad70cf 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -39,6 +39,7 @@ git_override( patches = [ "//bazel/bazel-orfs-patches:0001-stages-register-bazel-injected-vars-in-validator.patch", "//bazel/bazel-orfs-patches:0002-synth_partition-fix-SYNTH_SKIP_KEEP-truthy-check.patch", + "//bazel/bazel-orfs-patches:0003-synth_partition-parse-kept_modules-json-without-greedy-sed.patch", ], remote = BAZEL_ORFS_REMOTE, ) diff --git a/bazel/bazel-orfs-patches/0003-synth_partition-parse-kept_modules-json-without-greedy-sed.patch b/bazel/bazel-orfs-patches/0003-synth_partition-parse-kept_modules-json-without-greedy-sed.patch new file mode 100644 index 0000000000..be125434aa --- /dev/null +++ b/bazel/bazel-orfs-patches/0003-synth_partition-parse-kept_modules-json-without-greedy-sed.patch @@ -0,0 +1,20 @@ +diff --git a/synth_partition.sh b/synth_partition.sh +index 5fa420b..f37ca48 100755 +--- a/synth_partition.sh ++++ b/synth_partition.sh +@@ -17,9 +17,12 @@ NUM_PARTITIONS=${SYNTH_NUM_PARTITIONS:?} + KEPT_JSON="$RESULTS_DIR/kept_modules.json" + OUTPUT="$RESULTS_DIR/partition_${PARTITION_ID}.v" + +-# Parse module list from JSON using sed (avoids python wrapper issues) +-# JSON format: {"modules": ["mod1", "mod2", ...]} +-ALL_MODULES=$(sed 's/.*\[//;s/\].*//;s/"//g;s/,/\n/g;s/ //g' "$KEPT_JSON") ++# Parse module list from JSON. Module names can contain '[' and ']' ++# (slang elaborates parameterized instances to names like ++# 'foo$bar.gen_tiles[0].i_tile.gen_banks[3]'), so a greedy sed regex is ++# unsafe. Module names cannot contain '"', so extracting all quoted ++# strings and skipping the first ("modules" key) is correct. ++ALL_MODULES=$(grep -oE '"[^"]+"' "$KEPT_JSON" | tail -n +2 | sed 's/"//g') + + # When SYNTH_SKIP_KEEP=1, the keep-hierarchy discovery was skipped. + # Partitions read from canonical RTLIL and run full synthesis (coarse+fine). From bdab1d08f587b57339405a34c0d3399008032fb0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 5 May 2026 05:40:20 +0200 Subject: [PATCH 16/28] build: mark non-propagated MODULE.bazel decls as dev_dependency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When @orfs is fetched as a non-root dep (e.g. by tools/OpenROAD/MODULE.bazel), the downstream module brings its own openroad/qt-bazel/bazel-orfs/yosys-slang pins and orfs.default() configuration -- our overrides at root are duplicated or out of place. Previously tools/OpenROAD carried bazel-orfs-patches/0035 to strip those declarations from our MODULE.bazel at consumption time. With dev_dependency = True on the bazel_dep, use_extension, and register_toolchains lines that only matter at root, Bazel ignores them automatically when @orfs is non-root, so the patch becomes unnecessary. Verified at root with bazelisk query. Drops the unused makefile/makefile_yosys/pdk/variables_yaml overrides on orfs.default() too -- their defaults already point at @orfs//flow:* which resolves to our root labels. Signed-off-by: Øyvind Harboe --- MODULE.bazel | 42 ++++++++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/MODULE.bazel b/MODULE.bazel index 3645ad70cf..ace5e79daa 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -5,27 +5,37 @@ module( version = "0.0.1", ) -# --- Regular dependencies --- +# --- Regular dependencies (propagated to downstream consumers) --- bazel_dep(name = "rules_python", version = "1.8.5") bazel_dep(name = "rules_shell", version = "0.6.1") -bazel_dep(name = "toolchains_llvm", version = "1.5.0") -bazel_dep(name = "openroad") +# --- Dev dependencies (only honoured when @orfs is the root module) --- +# +# When @orfs is consumed as a non-root dep (e.g. by tools/OpenROAD), the +# downstream module brings its own openroad/qt-bazel/bazel-orfs/yosys-slang +# pins and orfs.default() configuration. Marking everything below as +# dev_dependency = True makes those declarations no-ops in that case, so +# our MODULE.bazel doesn't need to be patched at non-root consumption +# time. + +bazel_dep(name = "toolchains_llvm", version = "1.5.0", dev_dependency = True) + +bazel_dep(name = "openroad", dev_dependency = True) local_path_override( module_name = "openroad", path = "tools/OpenROAD", ) -bazel_dep(name = "qt-bazel") +bazel_dep(name = "qt-bazel", dev_dependency = True) git_override( module_name = "qt-bazel", commit = "886104974c2fd72439f2c33b5deebf0fe4649df7", remote = "https://github.com/The-OpenROAD-Project/qt_bazel_prebuilts", ) -bazel_dep(name = "bazel-orfs") -bazel_dep(name = "bazel-orfs-verilog") +bazel_dep(name = "bazel-orfs", dev_dependency = True) +bazel_dep(name = "bazel-orfs-verilog", dev_dependency = True) BAZEL_ORFS_COMMIT = "78f19f25cec73bdec3517a76465dec7ce17ce227" @@ -55,7 +65,7 @@ git_override( # that has the upstream Bazel build (povik/yosys-slang#310) and the # slang.so visibility fix (povik/yosys-slang#311). Submodules pull in # vendored slang and fmt sources. -bazel_dep(name = "yosys-slang") +bazel_dep(name = "yosys-slang", dev_dependency = True) git_override( module_name = "yosys-slang", commit = "7753ea70431d85929292b90c33b32f6dbdb3b048", @@ -65,13 +75,17 @@ git_override( # --- Extensions --- -llvm = use_extension("@toolchains_llvm//toolchain/extensions:llvm.bzl", "llvm") +llvm = use_extension( + "@toolchains_llvm//toolchain/extensions:llvm.bzl", + "llvm", + dev_dependency = True, +) llvm.toolchain( llvm_version = "20.1.8", ) use_repo(llvm, "llvm_toolchain") -register_toolchains("@llvm_toolchain//:all") +register_toolchains("@llvm_toolchain//:all", dev_dependency = True) python = use_extension("@rules_python//python/extensions:python.bzl", "python") python.toolchain( @@ -87,12 +101,12 @@ pip.parse( ) use_repo(pip, "orfs-pip") -orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories") +orfs = use_extension( + "@bazel-orfs//:extension.bzl", + "orfs_repositories", + dev_dependency = True, +) orfs.default( - makefile = "//flow:makefile", - makefile_yosys = "//flow:makefile_yosys", - pdk = "//flow:asap7", - variables_yaml = "//flow:scripts/variables.yaml", # Expose the yosys-slang plugin via YOSYS_PLUGIN_PATH so # SYNTH_HDL_FRONTEND=slang works for ibex, cva6, uart, etc. yosys_plugins = ["@yosys-slang//src/yosys_plugin:slang.so"], From 9058937de97648713661e7ba5f9527b98cf3bc91 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 5 May 2026 06:23:59 +0200 Subject: [PATCH 17/28] build: register VERILOG_FILES_BLACKBOX in variables.yaml MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's a generic ORFS convention used by hierarchical designs -- sky130hd/microwatt and sky130hd/chameleon append a glob of IPs/*.v to VERILOG_FILES via this variable. bazel-orfs's config_mk_parser puts it into the orfs_flow sources dict, where check_variables then rejects it because variables.yaml didn't list it. Add the entry so microwatt loads. (chameleon also references FP_PDN_RAIL_OFFSET/WIDTH, which are design-specific knobs read by chameleon's pdn.cfg only; those need the orfs_flow user_arguments path, not a variables.yaml entry.) Signed-off-by: Øyvind Harboe --- docs/user/FlowVariables.md | 2 ++ flow/scripts/variables.json | 6 ++++++ flow/scripts/variables.yaml | 8 ++++++++ 3 files changed, 16 insertions(+) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 80d3073bc5..11fd392985 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -324,6 +324,7 @@ configuration file. | USE_NEGOTIATION| Enable using negotiation legalizer for detailed placement.| 0| | VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| | | VERILOG_FILES| The path to the design Verilog/SystemVerilog files providing a description of modules.| | +| VERILOG_FILES_BLACKBOX| Verilog files (typically `IPs/*.v`) that are appended to VERILOG_FILES in hierarchical designs and treated as blackbox modules by yosys. Only used by config.mk; ORFS doesn't read it as an env var.| | | VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | | VERILOG_TOP_PARAMS| Apply toplevel params (if exist). Passed in as a list of key value pairs in tcl syntax; separated by spaces: PARAM1 VALUE1 PARAM2 VALUE2| | | VIA_IN_PIN_MAX_LAYER| Passed as -via_in_pin_top_layer to pin_access and detailed_route.| | @@ -376,6 +377,7 @@ configuration file. - [UNSET_ABC9_BOX_CELLS](#UNSET_ABC9_BOX_CELLS) - [VERILOG_DEFINES](#VERILOG_DEFINES) - [VERILOG_FILES](#VERILOG_FILES) +- [VERILOG_FILES_BLACKBOX](#VERILOG_FILES_BLACKBOX) - [VERILOG_INCLUDE_DIRS](#VERILOG_INCLUDE_DIRS) - [VERILOG_TOP_PARAMS](#VERILOG_TOP_PARAMS) - [YOSYS_FLAGS](#YOSYS_FLAGS) diff --git a/flow/scripts/variables.json b/flow/scripts/variables.json index 0c8e56ad77..0ac1e23518 100644 --- a/flow/scripts/variables.json +++ b/flow/scripts/variables.json @@ -1447,6 +1447,12 @@ "synth" ] }, + "VERILOG_FILES_BLACKBOX": { + "description": "Verilog files (typically `IPs/*.v`) that are appended to VERILOG_FILES in hierarchical designs and treated as blackbox modules by yosys. Only used by config.mk; ORFS doesn't read it as an env var.\n", + "stages": [ + "synth" + ] + }, "VERILOG_INCLUDE_DIRS": { "description": "Specifies the include directories for the Verilog input files.\n", "stages": [ diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index c8cbfb7898..6c8d2300a6 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -1585,3 +1585,11 @@ CDL_FILE: for generating Circuit Description Language output. stages: - final +VERILOG_FILES_BLACKBOX: + description: > + Verilog files (typically `IPs/*.v`) that are appended to + VERILOG_FILES in hierarchical designs and treated as blackbox + modules by yosys. Only used by config.mk; ORFS doesn't read it as + an env var. + stages: + - synth From 9253ea63f446608ed040d668c11b3907ab0c9377 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 5 May 2026 06:36:55 +0200 Subject: [PATCH 18/28] build: add user_arguments to orfs_design (patch + chameleon usage) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit bazel-orfs's orfs_flow already has a user_arguments parameter that bypasses the variables.yaml validator -- intended for project-specific env vars read only by user-supplied .tcl/.mk files. orfs_design didn't forward to it, so config.mk vars like FP_PDN_RAIL_OFFSET (read by chameleon's pdn.cfg, not by ORFS) were rejected. Patch 0004 adds a user_arguments arg to orfs_design that names the config.mk vars to lift out of the validated arguments dict and into orfs_flow's user_arguments dict. Mirrored in flow/designs/design.bzl. Used in flow/designs/sky130hd/chameleon to declare FP_PDN_RAIL_OFFSET and FP_PDN_RAIL_WIDTH as user-only -- chameleon now loads. Signed-off-by: Øyvind Harboe --- MODULE.bazel | 1 + ...-forward-user_arguments-to-orfs_flow.patch | 48 +++++++++++++++++++ flow/designs/design.bzl | 11 +++-- flow/designs/sky130hd/chameleon/BUILD.bazel | 8 +++- 4 files changed, 64 insertions(+), 4 deletions(-) create mode 100644 bazel/bazel-orfs-patches/0004-orfs_design-forward-user_arguments-to-orfs_flow.patch diff --git a/MODULE.bazel b/MODULE.bazel index ace5e79daa..f014d0e1de 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -50,6 +50,7 @@ git_override( "//bazel/bazel-orfs-patches:0001-stages-register-bazel-injected-vars-in-validator.patch", "//bazel/bazel-orfs-patches:0002-synth_partition-fix-SYNTH_SKIP_KEEP-truthy-check.patch", "//bazel/bazel-orfs-patches:0003-synth_partition-parse-kept_modules-json-without-greedy-sed.patch", + "//bazel/bazel-orfs-patches:0004-orfs_design-forward-user_arguments-to-orfs_flow.patch", ], remote = BAZEL_ORFS_REMOTE, ) diff --git a/bazel/bazel-orfs-patches/0004-orfs_design-forward-user_arguments-to-orfs_flow.patch b/bazel/bazel-orfs-patches/0004-orfs_design-forward-user_arguments-to-orfs_flow.patch new file mode 100644 index 0000000000..2d2a411d98 --- /dev/null +++ b/bazel/bazel-orfs-patches/0004-orfs_design-forward-user_arguments-to-orfs_flow.patch @@ -0,0 +1,48 @@ +diff --git a/private/orfs_design.bzl b/private/orfs_design.bzl +index 3a0f3c2..cb607fc 100644 +--- a/private/orfs_design.bzl ++++ b/private/orfs_design.bzl +@@ -44,7 +44,7 @@ def _convert_sources(sources, pkg): + result[var] = converted + return result + +-def orfs_design(name = None, platform = None, design = None, designs = None, mock_openroad = None, mock_yosys = None): # buildifier: disable=unused-variable ++def orfs_design(name = None, platform = None, design = None, designs = None, mock_openroad = None, mock_yosys = None, user_arguments = []): # buildifier: disable=unused-variable + """Create orfs_flow() targets for a design based on its parsed config.mk. + + Call this from a design's BUILD.bazel: +@@ -66,6 +66,12 @@ def orfs_design(name = None, platform = None, design = None, designs = None, moc + mock_yosys: Label for mock-yosys binary. When set, lint flow uses + this instead of real Yosys for synthesis. + Example: "//mock/yosys/src/bin:yosys". ++ user_arguments: List of variable names from config.mk that are ++ project-specific (read by user-supplied .tcl/.mk, not by ++ ORFS itself, e.g. FP_PDN_RAIL_OFFSET in a custom pdn.cfg). ++ Routed through orfs_flow(user_arguments=...) to bypass the ++ variables.yaml validator instead of being checked as known ++ ORFS arguments. + """ + if designs == None: + fail("orfs_design() requires designs argument: pass DESIGNS from @orfs_designs//:designs.bzl") +@@ -158,6 +164,13 @@ def orfs_design(name = None, platform = None, design = None, designs = None, moc + # Real flow — uses Docker image with real OpenROAD/Yosys + arguments = dict(config["arguments"]) + ++ # Move caller-flagged design-specific knobs out of arguments and into ++ # user_arguments so they bypass the variables.yaml validator. ++ user_args = {} ++ for var in user_arguments: ++ if var in arguments: ++ user_args[var] = arguments.pop(var) ++ + # Default SYNTH_NUM_PARTITIONS to a static value so that the action graph + # is identical across machines and remote cache hits are possible. Users + # who prefer local parallelism over caching can pass NUM_CPUS explicitly. +@@ -174,6 +187,7 @@ def orfs_design(name = None, platform = None, design = None, designs = None, moc + verilog_files = verilog_files, + pdk = "//flow:" + platform, + arguments = arguments, ++ user_arguments = user_args, + sources = sources, + macros = macros if macros else [], + stage_data = {"synth": extra_data} if extra_data else {}, diff --git a/flow/designs/design.bzl b/flow/designs/design.bzl index 64c2f7a27b..0f1189f216 100644 --- a/flow/designs/design.bzl +++ b/flow/designs/design.bzl @@ -14,10 +14,15 @@ _GROUPS = { "gds": (["gds", "gds.gz"], ["gds", "gds.gz"]), } -def design(): - """Standard BUILD body for flow/designs///.""" +def design(user_arguments = []): + """Standard BUILD body for flow/designs///. + + user_arguments: see orfs_design — list of config.mk var names that + are project-specific (read by the design's own .tcl/.mk, not by + ORFS) and should bypass the variables.yaml validator. + """ native.exports_files(native.glob(["*"])) - orfs_design(designs = DESIGNS) + orfs_design(designs = DESIGNS, user_arguments = user_arguments) def files(group, extra_srcs = None): """Public exports_files + named filegroup over conventional extensions.""" diff --git a/flow/designs/sky130hd/chameleon/BUILD.bazel b/flow/designs/sky130hd/chameleon/BUILD.bazel index fa2e42ab1a..e4fdadabc9 100644 --- a/flow/designs/sky130hd/chameleon/BUILD.bazel +++ b/flow/designs/sky130hd/chameleon/BUILD.bazel @@ -1,3 +1,9 @@ load("//flow/designs:design.bzl", "design") -design() +# FP_PDN_RAIL_{OFFSET,WIDTH} are read by chameleon's own pdn.cfg, not +# by ORFS itself — route them through user_arguments so the validator +# doesn't reject them as unknown ORFS variables. +design(user_arguments = [ + "FP_PDN_RAIL_OFFSET", + "FP_PDN_RAIL_WIDTH", +]) From 212b5dacc70fa7636e74a5b105ae878b0a04d94a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 5 May 2026 10:20:42 +0200 Subject: [PATCH 19/28] build: patch yosys 0.62 with the Tcl 9 use-after-free fix from main MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit YosysHQ/yosys 167c6c4 ("Replace deprecated Tcl API to fix use-after-free", povik, 2026-03-06) replaces five Tcl_SetResult(..., TCL_VOLATILE) callsites in kernel/tclapi.cc with Tcl_SetObjResult + Tcl_NewStringObj, the right idiom now that Tcl_SetResult is a macro under Tcl 9. Without it, rtlil::get_attr -string returns memory whose backing std::string has already been destructed, producing module names with stray control characters when synth_wrap_operators.tcl concatenates ${base}_${suffix}. Symptom: 'Found control character or space (0x18) in string \\K B-W_KOGGE_STONE'. Fix is in yosys main but not yet in BCR-tagged 0.62. Carry as patch on the BCR pin via single_version_override. Signed-off-by: Øyvind Harboe --- MODULE.bazel | 14 ++++ ...ecated-Tcl-API-to-fix-use-after-free.patch | 78 +++++++++++++++++++ bazel/yosys-patches/BUILD.bazel | 1 + 3 files changed, 93 insertions(+) create mode 100644 bazel/yosys-patches/0001-Replace-deprecated-Tcl-API-to-fix-use-after-free.patch create mode 100644 bazel/yosys-patches/BUILD.bazel diff --git a/MODULE.bazel b/MODULE.bazel index f014d0e1de..e947251181 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -74,6 +74,20 @@ git_override( remote = "https://github.com/povik/yosys-slang.git", ) +# YosysHQ/yosys 167c6c4 ("Replace deprecated Tcl API to fix use-after-free") +# fixes a Tcl 9 use-after-free in rtlil::get_attr/get_param that produces +# corrupted module names like '\K B-W_KOGGE_STONE' during ORFS-style +# wrapcell flows. The fix is in yosys main but not yet in the BCR-tagged +# 0.62; carry it as a patch until the next release lands. +single_version_override( + module_name = "yosys", + patch_strip = 1, + patches = [ + "//bazel/yosys-patches:0001-Replace-deprecated-Tcl-API-to-fix-use-after-free.patch", + ], + version = "0.62.bcr.2", +) + # --- Extensions --- llvm = use_extension( diff --git a/bazel/yosys-patches/0001-Replace-deprecated-Tcl-API-to-fix-use-after-free.patch b/bazel/yosys-patches/0001-Replace-deprecated-Tcl-API-to-fix-use-after-free.patch new file mode 100644 index 0000000000..96975fb0c5 --- /dev/null +++ b/bazel/yosys-patches/0001-Replace-deprecated-Tcl-API-to-fix-use-after-free.patch @@ -0,0 +1,78 @@ +From 167c6c45858fa637a872a57cdcdb758cd9e6c77a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Martin=20Povi=C5=A1er?= +Date: Fri, 6 Mar 2026 11:52:17 +0100 +Subject: [PATCH] Replace deprecated Tcl API to fix use-after-free + +Under Tcl 9.0 the Tcl_SetResult utility is a macro: + + #define Tcl_SetResult(interp, result, freeProc) \ + do { \ + const char *__result = result; \ + Tcl_FreeProc *__freeProc = freeProc; \ + Tcl_SetObjResult(interp, Tcl_NewStringObj(__result, -1)); \ + if (__result != NULL && __freeProc != NULL && __freeProc != TCL_VOLATILE) { \ + if (__freeProc == TCL_DYNAMIC) { \ + Tcl_Free((char *)__result); \ + } else { \ + (*__freeProc)((char *)__result); \ + } \ + } \ + } while(0) + +Temporaries constructed as part of the 'result' expression will be +dropped before the 'result' pointer is used. What was safe when +Tcl_SetResult was a function isn't safe with the macro definition. +Transition away from deprecated SetResult to calling +SetObjResult/MewStringObj directly. +--- + kernel/tclapi.cc | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc +index ec0483a4a02..9866f5c9820 100644 +--- a/kernel/tclapi.cc ++++ b/kernel/tclapi.cc +@@ -279,7 +279,7 @@ static int tcl_get_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar + ERROR("object not found") + + if (string_flag) { +- Tcl_SetResult(interp, (char *) obj->get_string_attribute(attr_id).c_str(), TCL_VOLATILE); ++ Tcl_SetObjResult(interp, Tcl_NewStringObj(obj->get_string_attribute(attr_id).c_str(), -1)); + } else if (int_flag || uint_flag || sint_flag) { + if (!obj->has_attribute(attr_id)) + ERROR("attribute missing (required for -int)"); +@@ -295,7 +295,7 @@ static int tcl_get_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar + if (!obj->has_attribute(attr_id)) + ERROR("attribute missing (required unless -bool or -string)") + +- Tcl_SetResult(interp, (char *) obj->attributes.at(attr_id).as_string().c_str(), TCL_VOLATILE); ++ Tcl_SetObjResult(interp, Tcl_NewStringObj(obj->attributes.at(attr_id).as_string().c_str(), -1)); + } + + return TCL_OK; +@@ -341,7 +341,7 @@ static int tcl_has_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar + if (!obj) + ERROR("object not found") + +- Tcl_SetResult(interp, (char *) std::to_string(obj->has_attribute(attr_id)).c_str(), TCL_VOLATILE); ++ Tcl_SetObjResult(interp, Tcl_NewStringObj(std::to_string(obj->has_attribute(attr_id)).c_str(), -1)); + return TCL_OK; + } + +@@ -465,14 +465,14 @@ static int tcl_get_param(ClientData, Tcl_Interp *interp, int argc, const char *a + const RTLIL::Const &value = cell->getParam(param_id); + + if (string_flag) { +- Tcl_SetResult(interp, (char *) value.decode_string().c_str(), TCL_VOLATILE); ++ Tcl_SetObjResult(interp, Tcl_NewStringObj(value.decode_string().c_str(), -1)); + } else if (int_flag || uint_flag || sint_flag) { + mp_int value_mp; + if (!const_to_mp_int(value, &value_mp, sint_flag, uint_flag)) + ERROR("bignum manipulation failed"); + Tcl_SetObjResult(interp, Tcl_NewBignumObj(&value_mp)); + } else { +- Tcl_SetResult(interp, (char *) value.as_string().c_str(), TCL_VOLATILE); ++ Tcl_SetObjResult(interp, Tcl_NewStringObj(value.as_string().c_str(), -1)); + } + return TCL_OK; + } diff --git a/bazel/yosys-patches/BUILD.bazel b/bazel/yosys-patches/BUILD.bazel new file mode 100644 index 0000000000..d518110449 --- /dev/null +++ b/bazel/yosys-patches/BUILD.bazel @@ -0,0 +1 @@ +exports_files(glob(["*.patch"])) From fe89d476c168ab452eff250d7532d6086e07a667 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 8 May 2026 14:23:20 +0200 Subject: [PATCH 20/28] deps: bump bazel-orfs, drop upstreamed patches MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bump bazel-orfs to b1ceeb28 (head of The-OpenROAD-Project/bazel-orfs#719, "feat: support archive_override for ORFS pin"). All four bazel-orfs patches carried in this PR are upstreamed there: * 0001-stages-register-bazel-injected-vars-in-validator.patch * 0002-synth_partition-fix-SYNTH_SKIP_KEEP-truthy-check.patch * 0003-synth_partition-parse-kept_modules-json-without-greedy-sed.patch * 0004-orfs_design-forward-user_arguments-to-orfs_flow.patch so the patch files and the bazel/bazel-orfs-patches/ directory are removed. Co-Authored-By: Claude Opus 4.7 (1M context) Signed-off-by: Øyvind Harboe --- MODULE.bazel | 9 +- MODULE.bazel.lock | 781 +++++++++++++++++- ...ter-bazel-injected-vars-in-validator.patch | 48 -- ...ion-fix-SYNTH_SKIP_KEEP-truthy-check.patch | 18 - ...kept_modules-json-without-greedy-sed.patch | 20 - ...-forward-user_arguments-to-orfs_flow.patch | 48 -- bazel/bazel-orfs-patches/BUILD.bazel | 1 - 7 files changed, 780 insertions(+), 145 deletions(-) delete mode 100644 bazel/bazel-orfs-patches/0001-stages-register-bazel-injected-vars-in-validator.patch delete mode 100644 bazel/bazel-orfs-patches/0002-synth_partition-fix-SYNTH_SKIP_KEEP-truthy-check.patch delete mode 100644 bazel/bazel-orfs-patches/0003-synth_partition-parse-kept_modules-json-without-greedy-sed.patch delete mode 100644 bazel/bazel-orfs-patches/0004-orfs_design-forward-user_arguments-to-orfs_flow.patch delete mode 100644 bazel/bazel-orfs-patches/BUILD.bazel diff --git a/MODULE.bazel b/MODULE.bazel index e947251181..bba38126b1 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -37,7 +37,7 @@ git_override( bazel_dep(name = "bazel-orfs", dev_dependency = True) bazel_dep(name = "bazel-orfs-verilog", dev_dependency = True) -BAZEL_ORFS_COMMIT = "78f19f25cec73bdec3517a76465dec7ce17ce227" +BAZEL_ORFS_COMMIT = "b1ceeb28fc41b80b1fa85032e0770203847d4ba7" BAZEL_ORFS_REMOTE = "https://github.com/The-OpenROAD-Project/bazel-orfs.git" @@ -45,13 +45,6 @@ BAZEL_ORFS_REMOTE = "https://github.com/The-OpenROAD-Project/bazel-orfs.git" git_override( module_name = "bazel-orfs", commit = BAZEL_ORFS_COMMIT, - patch_strip = 1, - patches = [ - "//bazel/bazel-orfs-patches:0001-stages-register-bazel-injected-vars-in-validator.patch", - "//bazel/bazel-orfs-patches:0002-synth_partition-fix-SYNTH_SKIP_KEEP-truthy-check.patch", - "//bazel/bazel-orfs-patches:0003-synth_partition-parse-kept_modules-json-without-greedy-sed.patch", - "//bazel/bazel-orfs-patches:0004-orfs_design-forward-user_arguments-to-orfs_flow.patch", - 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"recordedDirentsInputs": {}, "envVariables": {}, diff --git a/bazel/bazel-orfs-patches/0001-stages-register-bazel-injected-vars-in-validator.patch b/bazel/bazel-orfs-patches/0001-stages-register-bazel-injected-vars-in-validator.patch deleted file mode 100644 index 358eaa343a..0000000000 --- a/bazel/bazel-orfs-patches/0001-stages-register-bazel-injected-vars-in-validator.patch +++ /dev/null @@ -1,48 +0,0 @@ -diff --git a/private/stages.bzl b/private/stages.bzl -index 8c1391a..28e8afa 100644 ---- a/private/stages.bzl -+++ b/private/stages.bzl -@@ -6,9 +6,31 @@ load("//private:utils.bzl", "flatten", "set", "union") - # A stage argument is used in one or more stages. This is metainformation - # about the ORFS code that there is no known nice way for ORFS to - # provide. --BAZEL_VARIABLE_TO_STAGES = {} -+# -+# Variables auto-injected by bazel-orfs (not present in ORFS variables.yaml) -+# are registered here so that check_variables() does not flag them as -+# unknown when downstream callers see them in arguments. -+BAZEL_VARIABLE_TO_STAGES = { -+ # Set in orfs_design.bzl when SYNTH_HIERARCHICAL=1. -+ "SYNTH_NUM_PARTITIONS": ["synth"], -+} - --BAZEL_STAGE_TO_VARIABLES = {} -+BAZEL_STAGE_TO_VARIABLES = { -+ stage: [v for v, stages in BAZEL_VARIABLE_TO_STAGES.items() if stage in stages] -+ for stage in [ -+ "synth", -+ "floorplan", -+ "place", -+ "cts", -+ "grt", -+ "route", -+ "final", -+ "generate_abstract", -+ "generate_metadata", -+ "test", -+ "update_rules", -+ ] -+} - - ALL_STAGES = [ - "synth", -@@ -135,7 +157,8 @@ ORFS_STAGE_TO_VARIABLES = { - } - - ALL_STAGE_TO_VARIABLES = { -- stage: ORFS_STAGE_TO_VARIABLES.get(stage, []) -+ stage: ORFS_STAGE_TO_VARIABLES.get(stage, []) + -+ BAZEL_STAGE_TO_VARIABLES.get(stage, []) - for stage in ALL_STAGES - } - diff --git a/bazel/bazel-orfs-patches/0002-synth_partition-fix-SYNTH_SKIP_KEEP-truthy-check.patch b/bazel/bazel-orfs-patches/0002-synth_partition-fix-SYNTH_SKIP_KEEP-truthy-check.patch deleted file mode 100644 index 66516e89ef..0000000000 --- a/bazel/bazel-orfs-patches/0002-synth_partition-fix-SYNTH_SKIP_KEEP-truthy-check.patch +++ /dev/null @@ -1,18 +0,0 @@ -diff --git a/synth_partition.sh b/synth_partition.sh -index bf3deb5..5fa420b 100755 ---- a/synth_partition.sh -+++ b/synth_partition.sh -@@ -21,9 +21,11 @@ OUTPUT="$RESULTS_DIR/partition_${PARTITION_ID}.v" - # JSON format: {"modules": ["mod1", "mod2", ...]} - ALL_MODULES=$(sed 's/.*\[//;s/\].*//;s/"//g;s/,/\n/g;s/ //g' "$KEPT_JSON") - --# When SYNTH_SKIP_KEEP is set, the keep-hierarchy discovery was skipped. -+# When SYNTH_SKIP_KEEP=1, the keep-hierarchy discovery was skipped. - # Partitions read from canonical RTLIL and run full synthesis (coarse+fine). --if [ -n "${SYNTH_SKIP_KEEP:-}" ]; then -+# ORFS variables.yaml defaults SYNTH_SKIP_KEEP to "0", so test for "1" -+# explicitly rather than -n (which is true for any non-empty string). -+if [ "${SYNTH_SKIP_KEEP:-0}" = "1" ]; then - CHECKPOINT="$RESULTS_DIR/1_1_yosys_canonicalize.rtlil" - # Validate that every SYNTH_KEEP_MODULES entry exists in the canonical RTLIL - RTLIL_MODULES_FILE=$(mktemp) diff --git a/bazel/bazel-orfs-patches/0003-synth_partition-parse-kept_modules-json-without-greedy-sed.patch b/bazel/bazel-orfs-patches/0003-synth_partition-parse-kept_modules-json-without-greedy-sed.patch deleted file mode 100644 index be125434aa..0000000000 --- a/bazel/bazel-orfs-patches/0003-synth_partition-parse-kept_modules-json-without-greedy-sed.patch +++ /dev/null @@ -1,20 +0,0 @@ -diff --git a/synth_partition.sh b/synth_partition.sh -index 5fa420b..f37ca48 100755 ---- a/synth_partition.sh -+++ b/synth_partition.sh -@@ -17,9 +17,12 @@ NUM_PARTITIONS=${SYNTH_NUM_PARTITIONS:?} - KEPT_JSON="$RESULTS_DIR/kept_modules.json" - OUTPUT="$RESULTS_DIR/partition_${PARTITION_ID}.v" - --# Parse module list from JSON using sed (avoids python wrapper issues) --# JSON format: {"modules": ["mod1", "mod2", ...]} --ALL_MODULES=$(sed 's/.*\[//;s/\].*//;s/"//g;s/,/\n/g;s/ //g' "$KEPT_JSON") -+# Parse module list from JSON. Module names can contain '[' and ']' -+# (slang elaborates parameterized instances to names like -+# 'foo$bar.gen_tiles[0].i_tile.gen_banks[3]'), so a greedy sed regex is -+# unsafe. Module names cannot contain '"', so extracting all quoted -+# strings and skipping the first ("modules" key) is correct. -+ALL_MODULES=$(grep -oE '"[^"]+"' "$KEPT_JSON" | tail -n +2 | sed 's/"//g') - - # When SYNTH_SKIP_KEEP=1, the keep-hierarchy discovery was skipped. - # Partitions read from canonical RTLIL and run full synthesis (coarse+fine). diff --git a/bazel/bazel-orfs-patches/0004-orfs_design-forward-user_arguments-to-orfs_flow.patch b/bazel/bazel-orfs-patches/0004-orfs_design-forward-user_arguments-to-orfs_flow.patch deleted file mode 100644 index 2d2a411d98..0000000000 --- a/bazel/bazel-orfs-patches/0004-orfs_design-forward-user_arguments-to-orfs_flow.patch +++ /dev/null @@ -1,48 +0,0 @@ -diff --git a/private/orfs_design.bzl b/private/orfs_design.bzl -index 3a0f3c2..cb607fc 100644 ---- a/private/orfs_design.bzl -+++ b/private/orfs_design.bzl -@@ -44,7 +44,7 @@ def _convert_sources(sources, pkg): - result[var] = converted - return result - --def orfs_design(name = None, platform = None, design = None, designs = None, mock_openroad = None, mock_yosys = None): # buildifier: disable=unused-variable -+def orfs_design(name = None, platform = None, design = None, designs = None, mock_openroad = None, mock_yosys = None, user_arguments = []): # buildifier: disable=unused-variable - """Create orfs_flow() targets for a design based on its parsed config.mk. - - Call this from a design's BUILD.bazel: -@@ -66,6 +66,12 @@ def orfs_design(name = None, platform = None, design = None, designs = None, moc - mock_yosys: Label for mock-yosys binary. When set, lint flow uses - this instead of real Yosys for synthesis. - Example: "//mock/yosys/src/bin:yosys". -+ user_arguments: List of variable names from config.mk that are -+ project-specific (read by user-supplied .tcl/.mk, not by -+ ORFS itself, e.g. FP_PDN_RAIL_OFFSET in a custom pdn.cfg). -+ Routed through orfs_flow(user_arguments=...) to bypass the -+ variables.yaml validator instead of being checked as known -+ ORFS arguments. - """ - if designs == None: - fail("orfs_design() requires designs argument: pass DESIGNS from @orfs_designs//:designs.bzl") -@@ -158,6 +164,13 @@ def orfs_design(name = None, platform = None, design = None, designs = None, moc - # Real flow — uses Docker image with real OpenROAD/Yosys - arguments = dict(config["arguments"]) - -+ # Move caller-flagged design-specific knobs out of arguments and into -+ # user_arguments so they bypass the variables.yaml validator. -+ user_args = {} -+ for var in user_arguments: -+ if var in arguments: -+ user_args[var] = arguments.pop(var) -+ - # Default SYNTH_NUM_PARTITIONS to a static value so that the action graph - # is identical across machines and remote cache hits are possible. Users - # who prefer local parallelism over caching can pass NUM_CPUS explicitly. -@@ -174,6 +187,7 @@ def orfs_design(name = None, platform = None, design = None, designs = None, moc - verilog_files = verilog_files, - pdk = "//flow:" + platform, - arguments = arguments, -+ user_arguments = user_args, - sources = sources, - macros = macros if macros else [], - stage_data = {"synth": extra_data} if extra_data else {}, diff --git a/bazel/bazel-orfs-patches/BUILD.bazel b/bazel/bazel-orfs-patches/BUILD.bazel deleted file mode 100644 index d518110449..0000000000 --- a/bazel/bazel-orfs-patches/BUILD.bazel +++ /dev/null @@ -1 +0,0 @@ -exports_files(glob(["*.patch"])) From d308ca9ba0f8e8c61b2bdf1f6d60c6676f929bda Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 8 May 2026 14:30:04 +0200 Subject: [PATCH 21/28] deps: drop redundant yosys Tcl 9 patch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The carried patch (yosys upstream commit 167c6c4, "Replace deprecated Tcl API to fix use-after-free") was upstreamed into BCR yosys 0.62.bcr.2 via bazel-central-registry#8636. bazel-orfs already dropped the same patch in commit 78f19f25 (\"chore: bump yosys to 0.62.bcr.2 and drop carried patches\"); we forked from a state that pre-dated that absorption. yosys-slang stays — it's the runtime slang.so plugin we still need to build from source for SYNTH_HDL_FRONTEND=slang. OpenROAD's tools/OpenROAD/MODULE.bazel sidesteps both by pinning a pre-d11ce8a bazel-orfs that pulls yosys+slang out of the ORFS docker image. Co-Authored-By: Claude Opus 4.7 (1M context) Signed-off-by: Øyvind Harboe --- MODULE.bazel | 14 ---- ...ecated-Tcl-API-to-fix-use-after-free.patch | 78 ------------------- bazel/yosys-patches/BUILD.bazel | 1 - 3 files changed, 93 deletions(-) delete mode 100644 bazel/yosys-patches/0001-Replace-deprecated-Tcl-API-to-fix-use-after-free.patch delete mode 100644 bazel/yosys-patches/BUILD.bazel diff --git a/MODULE.bazel b/MODULE.bazel index bba38126b1..2f5972698d 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -67,20 +67,6 @@ git_override( remote = "https://github.com/povik/yosys-slang.git", ) -# YosysHQ/yosys 167c6c4 ("Replace deprecated Tcl API to fix use-after-free") -# fixes a Tcl 9 use-after-free in rtlil::get_attr/get_param that produces -# corrupted module names like '\K B-W_KOGGE_STONE' during ORFS-style -# wrapcell flows. The fix is in yosys main but not yet in the BCR-tagged -# 0.62; carry it as a patch until the next release lands. -single_version_override( - module_name = "yosys", - patch_strip = 1, - patches = [ - "//bazel/yosys-patches:0001-Replace-deprecated-Tcl-API-to-fix-use-after-free.patch", - ], - version = "0.62.bcr.2", -) - # --- Extensions --- llvm = use_extension( diff --git a/bazel/yosys-patches/0001-Replace-deprecated-Tcl-API-to-fix-use-after-free.patch b/bazel/yosys-patches/0001-Replace-deprecated-Tcl-API-to-fix-use-after-free.patch deleted file mode 100644 index 96975fb0c5..0000000000 --- a/bazel/yosys-patches/0001-Replace-deprecated-Tcl-API-to-fix-use-after-free.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 167c6c45858fa637a872a57cdcdb758cd9e6c77a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Martin=20Povi=C5=A1er?= -Date: Fri, 6 Mar 2026 11:52:17 +0100 -Subject: [PATCH] Replace deprecated Tcl API to fix use-after-free - -Under Tcl 9.0 the Tcl_SetResult utility is a macro: - - #define Tcl_SetResult(interp, result, freeProc) \ - do { \ - const char *__result = result; \ - Tcl_FreeProc *__freeProc = freeProc; \ - Tcl_SetObjResult(interp, Tcl_NewStringObj(__result, -1)); \ - if (__result != NULL && __freeProc != NULL && __freeProc != TCL_VOLATILE) { \ - if (__freeProc == TCL_DYNAMIC) { \ - Tcl_Free((char *)__result); \ - } else { \ - (*__freeProc)((char *)__result); \ - } \ - } \ - } while(0) - -Temporaries constructed as part of the 'result' expression will be -dropped before the 'result' pointer is used. What was safe when -Tcl_SetResult was a function isn't safe with the macro definition. -Transition away from deprecated SetResult to calling -SetObjResult/MewStringObj directly. ---- - kernel/tclapi.cc | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc -index ec0483a4a02..9866f5c9820 100644 ---- a/kernel/tclapi.cc -+++ b/kernel/tclapi.cc -@@ -279,7 +279,7 @@ static int tcl_get_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar - ERROR("object not found") - - if (string_flag) { -- Tcl_SetResult(interp, (char *) obj->get_string_attribute(attr_id).c_str(), TCL_VOLATILE); -+ Tcl_SetObjResult(interp, Tcl_NewStringObj(obj->get_string_attribute(attr_id).c_str(), -1)); - } else if (int_flag || uint_flag || sint_flag) { - if (!obj->has_attribute(attr_id)) - ERROR("attribute missing (required for -int)"); -@@ -295,7 +295,7 @@ static int tcl_get_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar - if (!obj->has_attribute(attr_id)) - ERROR("attribute missing (required unless -bool or -string)") - -- Tcl_SetResult(interp, (char *) obj->attributes.at(attr_id).as_string().c_str(), TCL_VOLATILE); -+ Tcl_SetObjResult(interp, Tcl_NewStringObj(obj->attributes.at(attr_id).as_string().c_str(), -1)); - } - - return TCL_OK; -@@ -341,7 +341,7 @@ static int tcl_has_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar - if (!obj) - ERROR("object not found") - -- Tcl_SetResult(interp, (char *) std::to_string(obj->has_attribute(attr_id)).c_str(), TCL_VOLATILE); -+ Tcl_SetObjResult(interp, Tcl_NewStringObj(std::to_string(obj->has_attribute(attr_id)).c_str(), -1)); - return TCL_OK; - } - -@@ -465,14 +465,14 @@ static int tcl_get_param(ClientData, Tcl_Interp *interp, int argc, const char *a - const RTLIL::Const &value = cell->getParam(param_id); - - if (string_flag) { -- Tcl_SetResult(interp, (char *) value.decode_string().c_str(), TCL_VOLATILE); -+ Tcl_SetObjResult(interp, Tcl_NewStringObj(value.decode_string().c_str(), -1)); - } else if (int_flag || uint_flag || sint_flag) { - mp_int value_mp; - if (!const_to_mp_int(value, &value_mp, sint_flag, uint_flag)) - ERROR("bignum manipulation failed"); - Tcl_SetObjResult(interp, Tcl_NewBignumObj(&value_mp)); - } else { -- Tcl_SetResult(interp, (char *) value.as_string().c_str(), TCL_VOLATILE); -+ Tcl_SetObjResult(interp, Tcl_NewStringObj(value.as_string().c_str(), -1)); - } - return TCL_OK; - } diff --git a/bazel/yosys-patches/BUILD.bazel b/bazel/yosys-patches/BUILD.bazel deleted file mode 100644 index d518110449..0000000000 --- a/bazel/yosys-patches/BUILD.bazel +++ /dev/null @@ -1 +0,0 @@ -exports_files(glob(["*.patch"])) From 735908f8ceee4af19063c7de444570aee6d74aac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Sat, 9 May 2026 16:52:54 +0200 Subject: [PATCH 22/28] bazel: make BUILD files self-documenting per hzeller's review MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Address hzeller's review feedback on PR #4208: 1. Replace opaque `orfs_design(designs = DESIGNS)` with explicit `orfs_design(config = "config.mk")` so BUILD files show what drives the build. The DESIGNS dict is baked into a generated wrapper in @orfs_designs//:designs.bzl. 2. Remove all `exports_files()` calls — the orfs_design macro now creates filegroups for design files (config, lef, lib, gds, verilog) with public visibility instead. 3. Source design BUILD files use `files("verilog")` macro which now creates filegroups without exports_files. The bazel-orfs API change is carried as a patch on the pinned commit; will be upstreamed to bazel-orfs once stable. Co-Authored-By: Claude Opus 4.6 (1M context) Signed-off-by: Øyvind Harboe --- MODULE.bazel | 2 + ...pt-config-mk-explicitly-drop-exports.patch | 107 ++++++++++++++++++ flow/BUILD.bazel | 7 -- flow/designs/asap7/aes-block/BUILD.bazel | 2 +- flow/designs/asap7/aes-mbff/BUILD.bazel | 2 +- flow/designs/asap7/aes/BUILD.bazel | 2 +- flow/designs/asap7/aes_lvt/BUILD.bazel | 2 +- flow/designs/asap7/cva6/BUILD.bazel | 2 +- flow/designs/asap7/ethmac/BUILD.bazel | 2 +- flow/designs/asap7/ethmac_lvt/BUILD.bazel | 2 +- flow/designs/asap7/gcd-ccs/BUILD.bazel | 2 +- flow/designs/asap7/gcd/BUILD.bazel | 2 +- flow/designs/asap7/ibex/BUILD.bazel | 2 +- flow/designs/asap7/jpeg/BUILD.bazel | 2 +- flow/designs/asap7/jpeg_lvt/BUILD.bazel | 2 +- flow/designs/asap7/minimal/BUILD.bazel | 7 +- flow/designs/asap7/mock-alu/BUILD.bazel | 2 +- flow/designs/asap7/mock-cpu/BUILD.bazel | 2 +- .../asap7/riscv32i-mock-sram/BUILD.bazel | 2 +- .../fakeram7_256x32/BUILD.bazel | 2 +- flow/designs/asap7/riscv32i/BUILD.bazel | 2 +- flow/designs/asap7/swerv_wrapper/BUILD.bazel | 2 +- flow/designs/asap7/uart/BUILD.bazel | 2 +- flow/designs/design.bzl | 42 ++++--- flow/designs/gf180/aes-hybrid/BUILD.bazel | 2 +- flow/designs/gf180/aes/BUILD.bazel | 2 +- flow/designs/gf180/ibex/BUILD.bazel | 2 +- flow/designs/gf180/jpeg/BUILD.bazel | 2 +- flow/designs/gf180/riscv32i/BUILD.bazel | 2 +- flow/designs/gf180/uart-blocks/BUILD.bazel | 2 +- .../gf180/uart-blocks/uart_rx/BUILD.bazel | 2 +- flow/designs/ihp-sg13g2/aes/BUILD.bazel | 2 +- flow/designs/ihp-sg13g2/gcd/BUILD.bazel | 2 +- .../ihp-sg13g2/i2c-gpio-expander/BUILD.bazel | 2 +- .../I2cDeviceCtrl/BUILD.bazel | 2 +- flow/designs/ihp-sg13g2/ibex/BUILD.bazel | 2 +- flow/designs/ihp-sg13g2/jpeg/BUILD.bazel | 2 +- flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel | 2 +- flow/designs/ihp-sg13g2/spi/BUILD.bazel | 2 +- flow/designs/nangate45/aes/BUILD.bazel | 2 +- flow/designs/nangate45/ariane133/BUILD.bazel | 2 +- flow/designs/nangate45/ariane136/BUILD.bazel | 2 +- .../nangate45/black_parrot/BUILD.bazel | 2 +- flow/designs/nangate45/bp_be_top/BUILD.bazel | 2 +- flow/designs/nangate45/bp_fe_top/BUILD.bazel | 2 +- .../nangate45/bp_multi_top/BUILD.bazel | 2 +- flow/designs/nangate45/bp_quad/BUILD.bazel | 2 +- .../nangate45/dynamic_node/BUILD.bazel | 2 +- flow/designs/nangate45/gcd/BUILD.bazel | 2 +- flow/designs/nangate45/ibex/BUILD.bazel | 2 +- flow/designs/nangate45/jpeg/BUILD.bazel | 2 +- .../nangate45/mempool_group/BUILD.bazel | 2 +- flow/designs/nangate45/swerv/BUILD.bazel | 2 +- .../nangate45/swerv_wrapper/BUILD.bazel | 2 +- flow/designs/nangate45/tinyRocket/BUILD.bazel | 2 +- flow/designs/sky130hd/aes/BUILD.bazel | 2 +- flow/designs/sky130hd/chameleon/BUILD.bazel | 2 +- flow/designs/sky130hd/gcd/BUILD.bazel | 2 +- flow/designs/sky130hd/ibex/BUILD.bazel | 2 +- flow/designs/sky130hd/jpeg/BUILD.bazel | 2 +- flow/designs/sky130hd/microwatt/BUILD.bazel | 2 +- flow/designs/sky130hd/riscv32i/BUILD.bazel | 2 +- flow/designs/sky130hs/aes/BUILD.bazel | 2 +- flow/designs/sky130hs/gcd/BUILD.bazel | 2 +- flow/designs/sky130hs/ibex/BUILD.bazel | 2 +- flow/designs/sky130hs/jpeg/BUILD.bazel | 2 +- flow/designs/sky130hs/riscv32i/BUILD.bazel | 2 +- .../hpdcache/rtl/include/BUILD.bazel | 9 +- .../src/common_cells/include/BUILD.bazel | 7 +- .../designs/src/cva6/core/include/BUILD.bazel | 9 +- flow/designs/src/ibex_sv/syn/BUILD.bazel | 4 - flow/designs/src/ibex_sv/syn/rtl/BUILD.bazel | 7 +- flow/designs/src/ibex_sv/vendor/BUILD.bazel | 4 - .../src/ibex_sv/vendor/lowrisc_ip/BUILD.bazel | 4 - .../vendor/lowrisc_ip/prim/BUILD.bazel | 4 - flow/designs/src/jpeg/include/BUILD.bazel | 7 +- .../designs/src/mempool_group/rtl/BUILD.bazel | 5 - .../src/mempool_group/rtl/axi/BUILD.bazel | 7 +- .../src/mempool_group/rtl/axi/src/BUILD.bazel | 7 +- .../rtl/cluster_interconnect/BUILD.bazel | 4 - .../rtl/cluster_interconnect/rtl/BUILD.bazel | 4 - .../rtl/tcdm_interconnect/BUILD.bazel | 7 +- .../variable_latency_interconnect/BUILD.bazel | 7 +- .../rtl/common_cells/BUILD.bazel | 7 +- .../rtl/common_cells/src/BUILD.bazel | 7 +- .../common_cells/src/deprecated/BUILD.bazel | 7 +- .../src/mempool_group/rtl/mempool/BUILD.bazel | 7 +- .../rtl/register_interface/BUILD.bazel | 4 - .../register_interface/include/BUILD.bazel | 5 - .../include/register_interface/BUILD.bazel | 7 +- .../src/mempool_group/rtl/snitch/BUILD.bazel | 4 - .../mempool_group/rtl/snitch/src/BUILD.bazel | 7 +- .../rtl/snitch/src/snitch_icache/BUILD.bazel | 7 +- .../rtl/tech_cells_generic/BUILD.bazel | 4 - .../rtl/tech_cells_generic/src/BUILD.bazel | 4 - .../tech_cells_generic/src/rtl/BUILD.bazel | 7 +- flow/designs/src/microwatt/IPs/BUILD.bazel | 7 +- flow/designs/src/mock-array/BUILD.bazel | 7 +- 98 files changed, 244 insertions(+), 232 deletions(-) create mode 100644 bazel/0001-orfs_design-accept-config-mk-explicitly-drop-exports.patch diff --git a/MODULE.bazel b/MODULE.bazel index 2f5972698d..b7b2a70e71 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -45,6 +45,8 @@ BAZEL_ORFS_REMOTE = "https://github.com/The-OpenROAD-Project/bazel-orfs.git" git_override( module_name = "bazel-orfs", commit = BAZEL_ORFS_COMMIT, + patches = ["//bazel:0001-orfs_design-accept-config-mk-explicitly-drop-exports.patch"], + patch_strip = 1, remote = BAZEL_ORFS_REMOTE, ) diff --git a/bazel/0001-orfs_design-accept-config-mk-explicitly-drop-exports.patch b/bazel/0001-orfs_design-accept-config-mk-explicitly-drop-exports.patch new file mode 100644 index 0000000000..d0d41d5dbb --- /dev/null +++ b/bazel/0001-orfs_design-accept-config-mk-explicitly-drop-exports.patch @@ -0,0 +1,107 @@ +diff --git a/private/designs.bzl b/private/designs.bzl +index e0bbc6c..9abde05 100644 +--- a/private/designs.bzl ++++ b/private/designs.bzl +@@ -146,8 +146,28 @@ def _orfs_designs_impl(repository_ctx): + "blocks": [], + } + +- # Generate designs.bzl +- bzl_content = "DESIGNS = %s\n" % repr(designs) ++ # Generate designs.bzl with both the raw DESIGNS dict (for backward ++ # compatibility) and an orfs_design() wrapper that bakes in DESIGNS ++ # so BUILD files can simply do: ++ # load("@orfs_designs//:designs.bzl", "orfs_design") ++ # orfs_design(config = "config.mk") ++ bzl_content = '''"""Auto-generated design configurations from config.mk files.""" ++ ++load("@bazel-orfs//private:orfs_design.bzl", _orfs_design = "orfs_design") ++ ++DESIGNS = %s ++ ++def orfs_design(config = "config.mk", **kwargs): ++ """Create orfs_flow() targets for this design. ++ ++ Args: ++ config: The config.mk file that drives this design. ++ Makes the BUILD file self-documenting. ++ **kwargs: Forwarded to the underlying orfs_design implementation ++ (platform, design, mock_openroad, mock_yosys, user_arguments). ++ """ ++ _orfs_design(config = config, designs = DESIGNS, **kwargs) ++''' % repr(designs) + repository_ctx.file("designs.bzl", bzl_content) + repository_ctx.file("BUILD.bazel", "") + +diff --git a/private/orfs_design.bzl b/private/orfs_design.bzl +index cb607fc..51e88f7 100644 +--- a/private/orfs_design.bzl ++++ b/private/orfs_design.bzl +@@ -1,7 +1,10 @@ + """Macro to create orfs_flow() targets from parsed config.mk data. + + Call orfs_design() from a design's BUILD.bazel to auto-generate +-orfs_flow() targets based on the design's config.mk. ++orfs_flow() targets based on the design's config.mk: ++ ++ load("@orfs_designs//:designs.bzl", "orfs_design") ++ orfs_design(config = "config.mk") + + The orfs_designs repository rule (designs.bzl) must be instantiated + first to parse all config.mk files and generate the DESIGNS dict. +@@ -44,22 +47,26 @@ def _convert_sources(sources, pkg): + result[var] = converted + return result + +-def orfs_design(name = None, platform = None, design = None, designs = None, mock_openroad = None, mock_yosys = None, user_arguments = []): # buildifier: disable=unused-variable ++def orfs_design(name = None, config = "config.mk", platform = None, design = None, designs = None, mock_openroad = None, mock_yosys = None, user_arguments = []): # buildifier: disable=unused-variable + """Create orfs_flow() targets for a design based on its parsed config.mk. + +- Call this from a design's BUILD.bazel: +- load("@bazel-orfs//:openroad.bzl", "orfs_design") +- load("@orfs_designs//:designs.bzl", "DESIGNS") +- orfs_design(designs = DESIGNS) ++ Usage: ++ ++ load("@orfs_designs//:designs.bzl", "orfs_design") ++ orfs_design(config = "config.mk") + + The platform and design are auto-detected from the package path + (flow/designs///). + + Args: + name: Unused, required by Bazel macro convention. ++ config: The config.mk file that drives this design. Makes the ++ BUILD file self-documenting about what configures the build. + platform: Override platform (default: from package path). + design: Override design nickname (default: from package path). + designs: The DESIGNS dict from the orfs_designs repository rule. ++ Supplied automatically by the generated wrapper in ++ @orfs_designs//:designs.bzl. + mock_openroad: Label for mock-openroad binary. When set, generates + lint flow targets (variant="lint") alongside real flow targets. + Example: "//mock/openroad/src/bin:openroad". +@@ -74,16 +81,17 @@ def orfs_design(name = None, platform = None, design = None, designs = None, moc + ORFS arguments. + """ + if designs == None: +- fail("orfs_design() requires designs argument: pass DESIGNS from @orfs_designs//:designs.bzl") ++ fail("orfs_design() requires designs: load orfs_design from @orfs_designs//:designs.bzl") + +- native.exports_files( +- native.glob(["*"]), +- visibility = ["//visibility:public"], +- ) ++ # Validate that the config file exists in this package ++ if not native.glob([config], allow_empty = True): ++ fail("orfs_design(): config file %s not found in %s" % (config, native.package_name())) + +- # Create filegroups for wildcard source patterns (e.g. ADDITIONAL_LEFS) ++ # Create filegroups for design files so they are accessible to ++ # orfs_flow() rules without using exports_files(). + existing_rules = native.existing_rules() + for fg_name, fg_glob in [ ++ ("design_config", ["*.mk", "*.sdc", "*.json", "*.cfg", "*.tcl", "*.def"]), + ("lef", ["*.lef"]), + ("lib", ["*.lib"]), + ("gds", ["*.gds.gz"]), diff --git a/flow/BUILD.bazel b/flow/BUILD.bazel index b6d4efc49f..f7e8f7c8a0 100644 --- a/flow/BUILD.bazel +++ b/flow/BUILD.bazel @@ -1,12 +1,5 @@ load("@bazel-orfs//:openroad.bzl", "orfs_pdk") -# Export platform files so designs can reference them directly via -# ADDITIONAL_LEFS, ADDITIONAL_LIBS, etc. from PLATFORM_DIR. -exports_files( - ["scripts/variables.yaml"] + glob(["platforms/**"]), - visibility = ["//visibility:public"], -) - # files shared between scripts/synth.sh and scripts/flow.sh steps MAKEFILE_SHARED = [ "scripts/variables.json", diff --git a/flow/designs/asap7/aes-block/BUILD.bazel b/flow/designs/asap7/aes-block/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/aes-block/BUILD.bazel +++ b/flow/designs/asap7/aes-block/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/aes-mbff/BUILD.bazel b/flow/designs/asap7/aes-mbff/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/aes-mbff/BUILD.bazel +++ b/flow/designs/asap7/aes-mbff/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/aes/BUILD.bazel b/flow/designs/asap7/aes/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/aes/BUILD.bazel +++ b/flow/designs/asap7/aes/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/aes_lvt/BUILD.bazel b/flow/designs/asap7/aes_lvt/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/aes_lvt/BUILD.bazel +++ b/flow/designs/asap7/aes_lvt/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/cva6/BUILD.bazel b/flow/designs/asap7/cva6/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/cva6/BUILD.bazel +++ b/flow/designs/asap7/cva6/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/ethmac/BUILD.bazel b/flow/designs/asap7/ethmac/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/ethmac/BUILD.bazel +++ b/flow/designs/asap7/ethmac/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/ethmac_lvt/BUILD.bazel b/flow/designs/asap7/ethmac_lvt/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/ethmac_lvt/BUILD.bazel +++ b/flow/designs/asap7/ethmac_lvt/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/gcd-ccs/BUILD.bazel b/flow/designs/asap7/gcd-ccs/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/gcd-ccs/BUILD.bazel +++ b/flow/designs/asap7/gcd-ccs/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/gcd/BUILD.bazel b/flow/designs/asap7/gcd/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/gcd/BUILD.bazel +++ b/flow/designs/asap7/gcd/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/ibex/BUILD.bazel b/flow/designs/asap7/ibex/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/ibex/BUILD.bazel +++ b/flow/designs/asap7/ibex/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/jpeg/BUILD.bazel b/flow/designs/asap7/jpeg/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/jpeg/BUILD.bazel +++ b/flow/designs/asap7/jpeg/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/jpeg_lvt/BUILD.bazel b/flow/designs/asap7/jpeg_lvt/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/jpeg_lvt/BUILD.bazel +++ b/flow/designs/asap7/jpeg_lvt/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/minimal/BUILD.bazel b/flow/designs/asap7/minimal/BUILD.bazel index 75ee41fcd8..1603de4372 100644 --- a/flow/designs/asap7/minimal/BUILD.bazel +++ b/flow/designs/asap7/minimal/BUILD.bazel @@ -1,3 +1,6 @@ -exports_files(glob(["*"])) - # Skipped: minimal has no VERILOG_FILES in config.mk (empty SDC test design). +filegroup( + name = "design_config", + srcs = glob(["*.mk", "*.sdc"], allow_empty = True), + visibility = ["//visibility:public"], +) diff --git a/flow/designs/asap7/mock-alu/BUILD.bazel b/flow/designs/asap7/mock-alu/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/mock-alu/BUILD.bazel +++ b/flow/designs/asap7/mock-alu/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/mock-cpu/BUILD.bazel b/flow/designs/asap7/mock-cpu/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/mock-cpu/BUILD.bazel +++ b/flow/designs/asap7/mock-cpu/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/riscv32i-mock-sram/BUILD.bazel b/flow/designs/asap7/riscv32i-mock-sram/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/riscv32i-mock-sram/BUILD.bazel +++ b/flow/designs/asap7/riscv32i-mock-sram/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel +++ b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/riscv32i/BUILD.bazel b/flow/designs/asap7/riscv32i/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/riscv32i/BUILD.bazel +++ b/flow/designs/asap7/riscv32i/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/swerv_wrapper/BUILD.bazel b/flow/designs/asap7/swerv_wrapper/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/swerv_wrapper/BUILD.bazel +++ b/flow/designs/asap7/swerv_wrapper/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/asap7/uart/BUILD.bazel b/flow/designs/asap7/uart/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/asap7/uart/BUILD.bazel +++ b/flow/designs/asap7/uart/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/design.bzl b/flow/designs/design.bzl index 0f1189f216..9d60aadae0 100644 --- a/flow/designs/design.bzl +++ b/flow/designs/design.bzl @@ -1,39 +1,35 @@ """BUILD.bazel boilerplate for flow/designs/.""" -load("@bazel-orfs//:openroad.bzl", "orfs_design") -load("@orfs_designs//:designs.bzl", "DESIGNS") +load("@orfs_designs//:designs.bzl", "orfs_design") -# Per filegroup target: (extensions in the filegroup, extensions in -# exports_files). bazel-orfs's config_mk_parser produces these target -# names from VERILOG_FILES wildcard patterns. +# Per filegroup target: extensions included in the filegroup. +# bazel-orfs's config_mk_parser produces these target names from +# VERILOG_FILES wildcard patterns. _GROUPS = { - "verilog": (["v", "sv"], ["v", "sv", "svh"]), - "include": (["v", "sv", "svh"], ["v", "sv", "svh"]), - "lef": (["lef"], ["lef"]), - "lib": (["lib"], ["lib"]), - "gds": (["gds", "gds.gz"], ["gds", "gds.gz"]), + "verilog": ["v", "sv"], + "include": ["v", "sv", "svh"], + "lef": ["lef"], + "lib": ["lib"], + "gds": ["gds", "gds.gz"], } -def design(user_arguments = []): +def design(config = "config.mk", user_arguments = []): """Standard BUILD body for flow/designs///. - user_arguments: see orfs_design — list of config.mk var names that - are project-specific (read by the design's own .tcl/.mk, not by - ORFS) and should bypass the variables.yaml validator. + Args: + config: The config.mk file that drives this design. + user_arguments: see orfs_design — list of config.mk var names that + are project-specific (read by the design's own .tcl/.mk, not by + ORFS) and should bypass the variables.yaml validator. """ - native.exports_files(native.glob(["*"])) - orfs_design(designs = DESIGNS, user_arguments = user_arguments) + orfs_design(config = config, user_arguments = user_arguments) def files(group, extra_srcs = None): - """Public exports_files + named filegroup over conventional extensions.""" - fg_exts, ex_exts = _GROUPS[group] - native.exports_files( - native.glob(["*.{}".format(e) for e in ex_exts], allow_empty = True), - visibility = ["//visibility:public"], - ) + """Named filegroup over conventional extensions.""" + exts = _GROUPS[group] native.filegroup( name = group, - srcs = native.glob(["*.{}".format(e) for e in fg_exts], allow_empty = True) + + srcs = native.glob(["*.{}".format(e) for e in exts], allow_empty = True) + (extra_srcs or []), visibility = ["//visibility:public"], ) diff --git a/flow/designs/gf180/aes-hybrid/BUILD.bazel b/flow/designs/gf180/aes-hybrid/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/gf180/aes-hybrid/BUILD.bazel +++ b/flow/designs/gf180/aes-hybrid/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/gf180/aes/BUILD.bazel b/flow/designs/gf180/aes/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/gf180/aes/BUILD.bazel +++ b/flow/designs/gf180/aes/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/gf180/ibex/BUILD.bazel b/flow/designs/gf180/ibex/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/gf180/ibex/BUILD.bazel +++ b/flow/designs/gf180/ibex/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/gf180/jpeg/BUILD.bazel b/flow/designs/gf180/jpeg/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/gf180/jpeg/BUILD.bazel +++ b/flow/designs/gf180/jpeg/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/gf180/riscv32i/BUILD.bazel b/flow/designs/gf180/riscv32i/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/gf180/riscv32i/BUILD.bazel +++ b/flow/designs/gf180/riscv32i/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/gf180/uart-blocks/BUILD.bazel b/flow/designs/gf180/uart-blocks/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/gf180/uart-blocks/BUILD.bazel +++ b/flow/designs/gf180/uart-blocks/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel b/flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel +++ b/flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/ihp-sg13g2/aes/BUILD.bazel b/flow/designs/ihp-sg13g2/aes/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/ihp-sg13g2/aes/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/aes/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/ihp-sg13g2/gcd/BUILD.bazel b/flow/designs/ihp-sg13g2/gcd/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/ihp-sg13g2/gcd/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/gcd/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel b/flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/ihp-sg13g2/ibex/BUILD.bazel b/flow/designs/ihp-sg13g2/ibex/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/ihp-sg13g2/ibex/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/ibex/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/ihp-sg13g2/jpeg/BUILD.bazel b/flow/designs/ihp-sg13g2/jpeg/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/ihp-sg13g2/jpeg/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/jpeg/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel b/flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/ihp-sg13g2/spi/BUILD.bazel b/flow/designs/ihp-sg13g2/spi/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/ihp-sg13g2/spi/BUILD.bazel +++ b/flow/designs/ihp-sg13g2/spi/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/aes/BUILD.bazel b/flow/designs/nangate45/aes/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/aes/BUILD.bazel +++ b/flow/designs/nangate45/aes/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/ariane133/BUILD.bazel b/flow/designs/nangate45/ariane133/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/ariane133/BUILD.bazel +++ b/flow/designs/nangate45/ariane133/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/ariane136/BUILD.bazel b/flow/designs/nangate45/ariane136/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/ariane136/BUILD.bazel +++ b/flow/designs/nangate45/ariane136/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/black_parrot/BUILD.bazel b/flow/designs/nangate45/black_parrot/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/black_parrot/BUILD.bazel +++ b/flow/designs/nangate45/black_parrot/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/bp_be_top/BUILD.bazel b/flow/designs/nangate45/bp_be_top/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/bp_be_top/BUILD.bazel +++ b/flow/designs/nangate45/bp_be_top/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/bp_fe_top/BUILD.bazel b/flow/designs/nangate45/bp_fe_top/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/bp_fe_top/BUILD.bazel +++ b/flow/designs/nangate45/bp_fe_top/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/bp_multi_top/BUILD.bazel b/flow/designs/nangate45/bp_multi_top/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/bp_multi_top/BUILD.bazel +++ b/flow/designs/nangate45/bp_multi_top/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/bp_quad/BUILD.bazel b/flow/designs/nangate45/bp_quad/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/bp_quad/BUILD.bazel +++ b/flow/designs/nangate45/bp_quad/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/dynamic_node/BUILD.bazel b/flow/designs/nangate45/dynamic_node/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/dynamic_node/BUILD.bazel +++ b/flow/designs/nangate45/dynamic_node/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/gcd/BUILD.bazel b/flow/designs/nangate45/gcd/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/gcd/BUILD.bazel +++ b/flow/designs/nangate45/gcd/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/ibex/BUILD.bazel b/flow/designs/nangate45/ibex/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/ibex/BUILD.bazel +++ b/flow/designs/nangate45/ibex/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/jpeg/BUILD.bazel b/flow/designs/nangate45/jpeg/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/jpeg/BUILD.bazel +++ b/flow/designs/nangate45/jpeg/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/mempool_group/BUILD.bazel b/flow/designs/nangate45/mempool_group/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/mempool_group/BUILD.bazel +++ b/flow/designs/nangate45/mempool_group/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/swerv/BUILD.bazel b/flow/designs/nangate45/swerv/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/swerv/BUILD.bazel +++ b/flow/designs/nangate45/swerv/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/swerv_wrapper/BUILD.bazel b/flow/designs/nangate45/swerv_wrapper/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/swerv_wrapper/BUILD.bazel +++ b/flow/designs/nangate45/swerv_wrapper/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/nangate45/tinyRocket/BUILD.bazel b/flow/designs/nangate45/tinyRocket/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/nangate45/tinyRocket/BUILD.bazel +++ b/flow/designs/nangate45/tinyRocket/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/sky130hd/aes/BUILD.bazel b/flow/designs/sky130hd/aes/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/sky130hd/aes/BUILD.bazel +++ b/flow/designs/sky130hd/aes/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/sky130hd/chameleon/BUILD.bazel b/flow/designs/sky130hd/chameleon/BUILD.bazel index e4fdadabc9..9d75a8d180 100644 --- a/flow/designs/sky130hd/chameleon/BUILD.bazel +++ b/flow/designs/sky130hd/chameleon/BUILD.bazel @@ -3,7 +3,7 @@ load("//flow/designs:design.bzl", "design") # FP_PDN_RAIL_{OFFSET,WIDTH} are read by chameleon's own pdn.cfg, not # by ORFS itself — route them through user_arguments so the validator # doesn't reject them as unknown ORFS variables. -design(user_arguments = [ +design(config = "config.mk", user_arguments = [ "FP_PDN_RAIL_OFFSET", "FP_PDN_RAIL_WIDTH", ]) diff --git a/flow/designs/sky130hd/gcd/BUILD.bazel b/flow/designs/sky130hd/gcd/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/sky130hd/gcd/BUILD.bazel +++ b/flow/designs/sky130hd/gcd/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/sky130hd/ibex/BUILD.bazel b/flow/designs/sky130hd/ibex/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/sky130hd/ibex/BUILD.bazel +++ b/flow/designs/sky130hd/ibex/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/sky130hd/jpeg/BUILD.bazel b/flow/designs/sky130hd/jpeg/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/sky130hd/jpeg/BUILD.bazel +++ b/flow/designs/sky130hd/jpeg/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/sky130hd/microwatt/BUILD.bazel b/flow/designs/sky130hd/microwatt/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/sky130hd/microwatt/BUILD.bazel +++ b/flow/designs/sky130hd/microwatt/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/sky130hd/riscv32i/BUILD.bazel b/flow/designs/sky130hd/riscv32i/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/sky130hd/riscv32i/BUILD.bazel +++ b/flow/designs/sky130hd/riscv32i/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/sky130hs/aes/BUILD.bazel b/flow/designs/sky130hs/aes/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/sky130hs/aes/BUILD.bazel +++ b/flow/designs/sky130hs/aes/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/sky130hs/gcd/BUILD.bazel b/flow/designs/sky130hs/gcd/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/sky130hs/gcd/BUILD.bazel +++ b/flow/designs/sky130hs/gcd/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/sky130hs/ibex/BUILD.bazel b/flow/designs/sky130hs/ibex/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/sky130hs/ibex/BUILD.bazel +++ b/flow/designs/sky130hs/ibex/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/sky130hs/jpeg/BUILD.bazel b/flow/designs/sky130hs/jpeg/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/sky130hs/jpeg/BUILD.bazel +++ b/flow/designs/sky130hs/jpeg/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/sky130hs/riscv32i/BUILD.bazel b/flow/designs/sky130hs/riscv32i/BUILD.bazel index fa2e42ab1a..527d6542e1 100644 --- a/flow/designs/sky130hs/riscv32i/BUILD.bazel +++ b/flow/designs/sky130hs/riscv32i/BUILD.bazel @@ -1,3 +1,3 @@ load("//flow/designs:design.bzl", "design") -design() +design(config = "config.mk") diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/BUILD.bazel index f31c831d67..d8101aa421 100644 --- a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/BUILD.bazel +++ b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/BUILD.bazel @@ -1,16 +1,11 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) - filegroup( name = "include", - srcs = glob(include = ["*.v", "*.sv", "*.svh"], allow_empty = True), + srcs = glob(["*.v", "*.sv", "*.svh"], allow_empty = True), visibility = ["//visibility:public"], ) filegroup( name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + srcs = glob(["*.v", "*.sv"], allow_empty = True), visibility = ["//visibility:public"], ) diff --git a/flow/designs/src/cva6/core/cvfpu/src/common_cells/include/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/common_cells/include/BUILD.bazel index 5ac3e69416..f5d11977e0 100644 --- a/flow/designs/src/cva6/core/cvfpu/src/common_cells/include/BUILD.bazel +++ b/flow/designs/src/cva6/core/cvfpu/src/common_cells/include/BUILD.bazel @@ -1,10 +1,5 @@ -exports_files( - glob(["**/*.v", "**/*.sv", "**/*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) - filegroup( name = "include", - srcs = glob(include = ["**/*.v", "**/*.sv", "**/*.svh"], allow_empty = True), + srcs = glob(["**/*.v", "**/*.sv", "**/*.svh"], allow_empty = True), visibility = ["//visibility:public"], ) diff --git a/flow/designs/src/cva6/core/include/BUILD.bazel b/flow/designs/src/cva6/core/include/BUILD.bazel index f31c831d67..d8101aa421 100644 --- a/flow/designs/src/cva6/core/include/BUILD.bazel +++ b/flow/designs/src/cva6/core/include/BUILD.bazel @@ -1,16 +1,11 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) - filegroup( name = "include", - srcs = glob(include = ["*.v", "*.sv", "*.svh"], allow_empty = True), + srcs = glob(["*.v", "*.sv", "*.svh"], allow_empty = True), visibility = ["//visibility:public"], ) filegroup( name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + srcs = glob(["*.v", "*.sv"], allow_empty = True), visibility = ["//visibility:public"], ) diff --git a/flow/designs/src/ibex_sv/syn/BUILD.bazel b/flow/designs/src/ibex_sv/syn/BUILD.bazel index 4b9b07d8a7..e69de29bb2 100644 --- a/flow/designs/src/ibex_sv/syn/BUILD.bazel +++ b/flow/designs/src/ibex_sv/syn/BUILD.bazel @@ -1,4 +0,0 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) diff --git a/flow/designs/src/ibex_sv/syn/rtl/BUILD.bazel b/flow/designs/src/ibex_sv/syn/rtl/BUILD.bazel index 4b9b07d8a7..115cf67d8f 100644 --- a/flow/designs/src/ibex_sv/syn/rtl/BUILD.bazel +++ b/flow/designs/src/ibex_sv/syn/rtl/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") diff --git a/flow/designs/src/ibex_sv/vendor/BUILD.bazel b/flow/designs/src/ibex_sv/vendor/BUILD.bazel index cf79c553b7..e69de29bb2 100644 --- a/flow/designs/src/ibex_sv/vendor/BUILD.bazel +++ b/flow/designs/src/ibex_sv/vendor/BUILD.bazel @@ -1,4 +0,0 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) diff --git a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/BUILD.bazel b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/BUILD.bazel index cf79c553b7..e69de29bb2 100644 --- a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/BUILD.bazel +++ b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/BUILD.bazel @@ -1,4 +0,0 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) diff --git a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/BUILD.bazel b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/BUILD.bazel index cf79c553b7..e69de29bb2 100644 --- a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/BUILD.bazel +++ b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/BUILD.bazel @@ -1,4 +0,0 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) diff --git a/flow/designs/src/jpeg/include/BUILD.bazel b/flow/designs/src/jpeg/include/BUILD.bazel index 2f7e49e5f9..8d02def028 100644 --- a/flow/designs/src/jpeg/include/BUILD.bazel +++ b/flow/designs/src/jpeg/include/BUILD.bazel @@ -1,10 +1,5 @@ -exports_files( - glob(["*.v", "*.sv"], allow_empty = True), - visibility = ["//visibility:public"], -) - filegroup( name = "include", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + srcs = glob(["*.v", "*.sv"], allow_empty = True), visibility = ["//visibility:public"], ) diff --git a/flow/designs/src/mempool_group/rtl/BUILD.bazel b/flow/designs/src/mempool_group/rtl/BUILD.bazel index 4839ec86b0..c9161cd38e 100644 --- a/flow/designs/src/mempool_group/rtl/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/BUILD.bazel @@ -1,8 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) - filegroup( name = "include", srcs = glob(["*.v", "*.sv", "*.svh"], allow_empty = True) + [ diff --git a/flow/designs/src/mempool_group/rtl/axi/BUILD.bazel b/flow/designs/src/mempool_group/rtl/axi/BUILD.bazel index cf79c553b7..115cf67d8f 100644 --- a/flow/designs/src/mempool_group/rtl/axi/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/axi/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") diff --git a/flow/designs/src/mempool_group/rtl/axi/src/BUILD.bazel b/flow/designs/src/mempool_group/rtl/axi/src/BUILD.bazel index cf79c553b7..115cf67d8f 100644 --- a/flow/designs/src/mempool_group/rtl/axi/src/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/axi/src/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/BUILD.bazel b/flow/designs/src/mempool_group/rtl/cluster_interconnect/BUILD.bazel index cf79c553b7..e69de29bb2 100644 --- a/flow/designs/src/mempool_group/rtl/cluster_interconnect/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/cluster_interconnect/BUILD.bazel @@ -1,4 +0,0 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/BUILD.bazel b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/BUILD.bazel index cf79c553b7..e69de29bb2 100644 --- a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/BUILD.bazel @@ -1,4 +0,0 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/BUILD.bazel b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/BUILD.bazel index cf79c553b7..115cf67d8f 100644 --- a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/BUILD.bazel b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/BUILD.bazel index cf79c553b7..115cf67d8f 100644 --- a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") diff --git a/flow/designs/src/mempool_group/rtl/common_cells/BUILD.bazel b/flow/designs/src/mempool_group/rtl/common_cells/BUILD.bazel index cf79c553b7..115cf67d8f 100644 --- a/flow/designs/src/mempool_group/rtl/common_cells/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/common_cells/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/BUILD.bazel b/flow/designs/src/mempool_group/rtl/common_cells/src/BUILD.bazel index cf79c553b7..115cf67d8f 100644 --- a/flow/designs/src/mempool_group/rtl/common_cells/src/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/BUILD.bazel b/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/BUILD.bazel index cf79c553b7..115cf67d8f 100644 --- a/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") diff --git a/flow/designs/src/mempool_group/rtl/mempool/BUILD.bazel b/flow/designs/src/mempool_group/rtl/mempool/BUILD.bazel index cf79c553b7..115cf67d8f 100644 --- a/flow/designs/src/mempool_group/rtl/mempool/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/mempool/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") diff --git a/flow/designs/src/mempool_group/rtl/register_interface/BUILD.bazel b/flow/designs/src/mempool_group/rtl/register_interface/BUILD.bazel index cf79c553b7..e69de29bb2 100644 --- a/flow/designs/src/mempool_group/rtl/register_interface/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/register_interface/BUILD.bazel @@ -1,4 +0,0 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) diff --git a/flow/designs/src/mempool_group/rtl/register_interface/include/BUILD.bazel b/flow/designs/src/mempool_group/rtl/register_interface/include/BUILD.bazel index 0127fa1306..4199700eac 100644 --- a/flow/designs/src/mempool_group/rtl/register_interface/include/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/register_interface/include/BUILD.bazel @@ -1,8 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) - filegroup( name = "include", srcs = glob(["*.v", "*.sv", "*.svh"], allow_empty = True) + [ diff --git a/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/BUILD.bazel b/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/BUILD.bazel index cf79c553b7..115cf67d8f 100644 --- a/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") diff --git a/flow/designs/src/mempool_group/rtl/snitch/BUILD.bazel b/flow/designs/src/mempool_group/rtl/snitch/BUILD.bazel index cf79c553b7..e69de29bb2 100644 --- a/flow/designs/src/mempool_group/rtl/snitch/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/snitch/BUILD.bazel @@ -1,4 +0,0 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/BUILD.bazel b/flow/designs/src/mempool_group/rtl/snitch/src/BUILD.bazel index cf79c553b7..115cf67d8f 100644 --- a/flow/designs/src/mempool_group/rtl/snitch/src/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/snitch/src/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/BUILD.bazel b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/BUILD.bazel index cf79c553b7..115cf67d8f 100644 --- a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") diff --git a/flow/designs/src/mempool_group/rtl/tech_cells_generic/BUILD.bazel b/flow/designs/src/mempool_group/rtl/tech_cells_generic/BUILD.bazel index cf79c553b7..e69de29bb2 100644 --- a/flow/designs/src/mempool_group/rtl/tech_cells_generic/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/tech_cells_generic/BUILD.bazel @@ -1,4 +0,0 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) diff --git a/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/BUILD.bazel b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/BUILD.bazel index cf79c553b7..e69de29bb2 100644 --- a/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/BUILD.bazel @@ -1,4 +0,0 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) diff --git a/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/BUILD.bazel b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/BUILD.bazel index cf79c553b7..115cf67d8f 100644 --- a/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/BUILD.bazel +++ b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*.v", "*.sv", "*.svh"], allow_empty = True), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") diff --git a/flow/designs/src/microwatt/IPs/BUILD.bazel b/flow/designs/src/microwatt/IPs/BUILD.bazel index de61a2428b..6a2b3ec4f1 100644 --- a/flow/designs/src/microwatt/IPs/BUILD.bazel +++ b/flow/designs/src/microwatt/IPs/BUILD.bazel @@ -1,8 +1,3 @@ -exports_files( - glob(["*"]), - visibility = ["//visibility:public"], -) - filegroup( name = "IPs", srcs = glob(["*"]), @@ -11,6 +6,6 @@ filegroup( filegroup( name = "verilog", - srcs = glob(include = ["*.v", "*.sv"], allow_empty = True), + srcs = glob(["*.v", "*.sv"], allow_empty = True), visibility = ["//visibility:public"], ) diff --git a/flow/designs/src/mock-array/BUILD.bazel b/flow/designs/src/mock-array/BUILD.bazel index 50d9202992..115cf67d8f 100644 --- a/flow/designs/src/mock-array/BUILD.bazel +++ b/flow/designs/src/mock-array/BUILD.bazel @@ -1,4 +1,3 @@ -exports_files( - glob(["*"]), - visibility = ["//visibility:public"], -) +load("//flow/designs:design.bzl", "files") + +files("verilog") From 4912278ea6ea9be795000ae125da39ce00b62744 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Sat, 9 May 2026 16:54:54 +0200 Subject: [PATCH 23/28] bazel: rename BUILD.bazel to BUILD for consistency with OpenROAD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Match the naming convention used in tools/OpenROAD. Co-Authored-By: Claude Opus 4.6 (1M context) Signed-off-by: Øyvind Harboe --- BUILD.bazel => BUILD | 0 MODULE.bazel | 2 +- WORKSPACE.bazel => WORKSPACE | 0 flow/{BUILD.bazel => BUILD} | 0 flow/designs/BUILD | 1 + flow/designs/BUILD.bazel | 1 - .../asap7/aes-block/{BUILD.bazel => BUILD} | 0 .../asap7/aes-mbff/{BUILD.bazel => BUILD} | 0 flow/designs/asap7/aes/{BUILD.bazel => BUILD} | 0 .../asap7/aes_lvt/{BUILD.bazel => BUILD} | 0 .../designs/asap7/cva6/{BUILD.bazel => BUILD} | 0 .../asap7/ethmac/{BUILD.bazel => BUILD} | 0 .../asap7/ethmac_lvt/{BUILD.bazel => BUILD} | 0 .../asap7/gcd-ccs/{BUILD.bazel => BUILD} | 0 flow/designs/asap7/gcd/BUILD | 21 ++----------------- .../asap7/{gcd/BUILD.bazel => ibex/BUILD} | 0 .../asap7/{ibex/BUILD.bazel => jpeg/BUILD} | 0 .../{jpeg/BUILD.bazel => jpeg_lvt/BUILD} | 0 .../asap7/minimal/{BUILD.bazel => BUILD} | 0 .../{jpeg_lvt/BUILD.bazel => mock-alu/BUILD} | 0 .../{mock-alu/BUILD.bazel => mock-cpu/BUILD} | 0 .../BUILD.bazel => riscv32i-mock-sram/BUILD} | 0 .../{BUILD.bazel => fakeram7_256x32/BUILD} | 0 .../BUILD.bazel => riscv32i/BUILD} | 0 .../BUILD.bazel => swerv_wrapper/BUILD} | 0 .../swerv_wrapper/lef/{BUILD.bazel => BUILD} | 0 .../swerv_wrapper/lib/{BUILD.bazel => BUILD} | 0 .../{swerv_wrapper/BUILD.bazel => uart/BUILD} | 0 flow/designs/design.bzl | 2 +- .../BUILD.bazel => gf180/aes-hybrid/BUILD} | 0 .../{aes-hybrid/BUILD.bazel => aes/BUILD} | 0 .../gf180/{aes/BUILD.bazel => ibex/BUILD} | 0 .../gf180/{ibex/BUILD.bazel => jpeg/BUILD} | 0 .../{jpeg/BUILD.bazel => riscv32i/BUILD} | 0 .../BUILD.bazel => uart-blocks/BUILD} | 0 .../{BUILD.bazel => uart_rx/BUILD} | 0 .../BUILD.bazel => ihp-sg13g2/aes/BUILD} | 0 .../ihp-sg13g2/{aes/BUILD.bazel => gcd/BUILD} | 0 .../BUILD.bazel => i2c-gpio-expander/BUILD} | 0 .../{BUILD.bazel => I2cDeviceCtrl/BUILD} | 0 .../I2cDeviceCtrl/BUILD.bazel => ibex/BUILD} | 0 .../{ibex/BUILD.bazel => jpeg/BUILD} | 0 .../{jpeg/BUILD.bazel => riscv32i/BUILD} | 0 .../{riscv32i/BUILD.bazel => spi/BUILD} | 0 .../spi/BUILD.bazel => nangate45/aes/BUILD} | 0 .../{aes/BUILD.bazel => ariane133/BUILD} | 0 .../BUILD.bazel => ariane136/BUILD} | 0 .../BUILD.bazel => black_parrot/BUILD} | 0 .../BUILD.bazel => bp_be_top/BUILD} | 0 .../BUILD.bazel => bp_fe_top/BUILD} | 0 .../BUILD.bazel => bp_multi_top/BUILD} | 0 .../BUILD.bazel => bp_quad/BUILD} | 0 .../BUILD.bazel => dynamic_node/BUILD} | 0 .../{dynamic_node/BUILD.bazel => gcd/BUILD} | 0 .../nangate45/{gcd/BUILD.bazel => ibex/BUILD} | 0 .../{ibex/BUILD.bazel => jpeg/BUILD} | 0 .../{jpeg/BUILD.bazel => mempool_group/BUILD} | 0 .../BUILD.bazel => swerv/BUILD} | 0 .../BUILD.bazel => swerv_wrapper/BUILD} | 0 .../BUILD.bazel => tinyRocket/BUILD} | 0 .../BUILD.bazel => sky130hd/aes/BUILD} | 0 .../sky130hd/chameleon/{BUILD.bazel => BUILD} | 0 .../chameleon/gds/{BUILD.bazel => BUILD} | 0 .../chameleon/lef/{BUILD.bazel => BUILD} | 0 .../sky130hd/{aes/BUILD.bazel => gcd/BUILD} | 0 .../sky130hd/{gcd/BUILD.bazel => ibex/BUILD} | 0 .../sky130hd/{ibex/BUILD.bazel => jpeg/BUILD} | 0 .../{jpeg/BUILD.bazel => microwatt/BUILD} | 0 .../microwatt/gds/{BUILD.bazel => BUILD} | 0 .../microwatt/lef/{BUILD.bazel => BUILD} | 0 .../microwatt/lib/{BUILD.bazel => BUILD} | 0 .../{microwatt/BUILD.bazel => riscv32i/BUILD} | 0 .../BUILD.bazel => sky130hs/aes/BUILD} | 0 .../sky130hs/{aes/BUILD.bazel => gcd/BUILD} | 0 .../sky130hs/{gcd/BUILD.bazel => ibex/BUILD} | 0 .../sky130hs/{ibex/BUILD.bazel => jpeg/BUILD} | 0 .../{jpeg/BUILD.bazel => riscv32i/BUILD} | 0 flow/designs/sky130hs/riscv32i/BUILD.bazel | 3 --- flow/designs/src/aes/{BUILD.bazel => BUILD} | 0 .../designs/src/ariane/{BUILD.bazel => BUILD} | 0 .../src/ariane133/{BUILD.bazel => BUILD} | 0 .../src/ariane136/{BUILD.bazel => BUILD} | 0 .../src/black_parrot/{BUILD.bazel => BUILD} | 0 .../src/bp_be_top/{BUILD.bazel => BUILD} | 0 .../src/bp_fe_top/{BUILD.bazel => BUILD} | 0 .../src/bp_multi_top/{BUILD.bazel => BUILD} | 0 .../src/bp_quad/{BUILD.bazel => BUILD} | 0 .../APB_sys_0/{BUILD.bazel => BUILD} | 0 .../AHB_sys_0/{BUILD.bazel => BUILD} | 0 .../src/chameleon/{BUILD.bazel => BUILD} | 0 .../src/chameleon/IPs/{BUILD.bazel => BUILD} | 0 .../IPs/apb2i2c/{BUILD.bazel => BUILD} | 0 .../src/chameleon/acc/{BUILD.bazel => BUILD} | 0 .../src/chameleon/ibex/{BUILD.bazel => BUILD} | 0 .../ibex/models/{BUILD.bazel => BUILD} | 0 .../designs/src/coyote/{BUILD.bazel => BUILD} | 0 flow/designs/src/cva6/{BUILD.bazel => BUILD} | 0 .../src/cva6/common/{BUILD.bazel => BUILD} | 0 .../cva6/common/local/{BUILD.bazel => BUILD} | 0 .../common/local/util/{BUILD.bazel => BUILD} | 0 .../src/cva6/core/{BUILD.bazel => BUILD} | 0 .../cache_subsystem/{BUILD.bazel => BUILD} | 0 .../hpdcache/{BUILD.bazel => BUILD} | 0 .../hpdcache/rtl/{BUILD.bazel => BUILD} | 0 .../rtl/include/{BUILD.bazel => BUILD} | 0 .../hpdcache/rtl/src/{BUILD.bazel => BUILD} | 0 .../rtl/src/common/{BUILD.bazel => BUILD} | 0 .../src/common/macros/{BUILD.bazel => BUILD} | 0 .../macros/blackbox/{BUILD.bazel => BUILD} | 0 .../src/hwpf_stride/{BUILD.bazel => BUILD} | 0 .../rtl/src/utils/{BUILD.bazel => BUILD} | 0 .../cva6/core/cva6_mmu/{BUILD.bazel => BUILD} | 0 .../cva6/core/cvfpu/{BUILD.bazel => BUILD} | 0 .../core/cvfpu/src/{BUILD.bazel => BUILD} | 0 .../src/common_cells/{BUILD.bazel => BUILD} | 0 .../include/{BUILD.bazel => BUILD} | 0 .../fpu_div_sqrt_mvp/{BUILD.bazel => BUILD} | 0 .../hdl/{BUILD.bazel => BUILD} | 0 .../core/cvxif_example/{BUILD.bazel => BUILD} | 0 .../include/{BUILD.bazel => BUILD} | 0 .../cva6/core/frontend/{BUILD.bazel => BUILD} | 0 .../cva6/core/include/{BUILD.bazel => BUILD} | 0 .../src/cva6/core/pmp/{BUILD.bazel => BUILD} | 0 .../cva6/core/pmp/src/{BUILD.bazel => BUILD} | 0 .../src/cva6/vendor/{BUILD.bazel => BUILD} | 0 .../pulp-platform/{BUILD.bazel => BUILD} | 0 .../pulp-platform/axi/{BUILD.bazel => BUILD} | 0 .../axi/src/{BUILD.bazel => BUILD} | 0 .../common_cells/{BUILD.bazel => BUILD} | 0 .../common_cells/src/{BUILD.bazel => BUILD} | 0 .../tech_cells_generic/{BUILD.bazel => BUILD} | 0 .../src/{BUILD.bazel => BUILD} | 0 .../src/rtl/{BUILD.bazel => BUILD} | 0 .../src/dynamic_node/{BUILD.bazel => BUILD} | 0 .../designs/src/ethmac/{BUILD.bazel => BUILD} | 0 flow/designs/src/fifo/{BUILD.bazel => BUILD} | 0 flow/designs/src/gcd/{BUILD.bazel => BUILD} | 0 .../src/ibex_sv/{BUILD.bazel => BUILD} | 0 .../src/ibex_sv/syn/{BUILD.bazel => BUILD} | 0 .../ibex_sv/syn/rtl/{BUILD.bazel => BUILD} | 0 .../src/ibex_sv/vendor/{BUILD.bazel => BUILD} | 0 .../vendor/lowrisc_ip/{BUILD.bazel => BUILD} | 0 .../lowrisc_ip/prim/{BUILD.bazel => BUILD} | 0 .../prim/rtl/{BUILD.bazel => BUILD} | 0 flow/designs/src/jpeg/{BUILD.bazel => BUILD} | 0 .../src/jpeg/include/{BUILD.bazel => BUILD} | 0 .../src/mempool_group/{BUILD.bazel => BUILD} | 0 .../mempool_group/rtl/{BUILD.bazel => BUILD} | 0 .../rtl/axi/{BUILD.bazel => BUILD} | 0 .../rtl/axi/src/{BUILD.bazel => BUILD} | 0 .../{BUILD.bazel => BUILD} | 0 .../rtl/{BUILD.bazel => BUILD} | 0 .../tcdm_interconnect/{BUILD.bazel => BUILD} | 0 .../{BUILD.bazel => BUILD} | 0 .../rtl/common_cells/{BUILD.bazel => BUILD} | 0 .../common_cells/src/{BUILD.bazel => BUILD} | 0 .../src/deprecated/{BUILD.bazel => BUILD} | 0 .../rtl/mempool/{BUILD.bazel => BUILD} | 0 .../register_interface/{BUILD.bazel => BUILD} | 0 .../include/{BUILD.bazel => BUILD} | 0 .../register_interface/{BUILD.bazel => BUILD} | 0 .../rtl/snitch/{BUILD.bazel => BUILD} | 0 .../rtl/snitch/src/{BUILD.bazel => BUILD} | 0 .../src/snitch_icache/{BUILD.bazel => BUILD} | 0 .../tech_cells_generic/{BUILD.bazel => BUILD} | 0 .../src/{BUILD.bazel => BUILD} | 0 .../src/rtl/{BUILD.bazel => BUILD} | 0 .../src/microwatt/{BUILD.bazel => BUILD} | 0 .../src/microwatt/IPs/{BUILD.bazel => BUILD} | 0 .../src/mock-alu/{BUILD.bazel => BUILD} | 0 .../src/mock-array/{BUILD.bazel => BUILD} | 0 .../src/riscv32i/{BUILD.bazel => BUILD} | 0 flow/designs/src/spi/{BUILD.bazel => BUILD} | 0 flow/designs/src/swerv/{BUILD.bazel => BUILD} | 0 .../src/tinyRocket/{BUILD.bazel => BUILD} | 0 .../src/uart-no-param/{BUILD.bazel => BUILD} | 0 flow/designs/src/uart/{BUILD.bazel => BUILD} | 0 flow/util/{BUILD.bazel => BUILD} | 0 178 files changed, 5 insertions(+), 25 deletions(-) rename BUILD.bazel => BUILD (100%) rename WORKSPACE.bazel => WORKSPACE (100%) rename flow/{BUILD.bazel => BUILD} (100%) create mode 100644 flow/designs/BUILD delete mode 100644 flow/designs/BUILD.bazel rename flow/designs/asap7/aes-block/{BUILD.bazel => BUILD} (100%) rename flow/designs/asap7/aes-mbff/{BUILD.bazel => BUILD} (100%) rename flow/designs/asap7/aes/{BUILD.bazel => BUILD} (100%) rename flow/designs/asap7/aes_lvt/{BUILD.bazel => BUILD} (100%) rename flow/designs/asap7/cva6/{BUILD.bazel => BUILD} (100%) rename flow/designs/asap7/ethmac/{BUILD.bazel => BUILD} (100%) rename flow/designs/asap7/ethmac_lvt/{BUILD.bazel => BUILD} (100%) rename flow/designs/asap7/gcd-ccs/{BUILD.bazel => BUILD} (100%) rename flow/designs/asap7/{gcd/BUILD.bazel => ibex/BUILD} (100%) rename flow/designs/asap7/{ibex/BUILD.bazel => jpeg/BUILD} (100%) rename flow/designs/asap7/{jpeg/BUILD.bazel => jpeg_lvt/BUILD} (100%) rename flow/designs/asap7/minimal/{BUILD.bazel => BUILD} (100%) rename flow/designs/asap7/{jpeg_lvt/BUILD.bazel => mock-alu/BUILD} (100%) rename flow/designs/asap7/{mock-alu/BUILD.bazel => mock-cpu/BUILD} (100%) rename flow/designs/asap7/{mock-cpu/BUILD.bazel => riscv32i-mock-sram/BUILD} (100%) rename flow/designs/asap7/riscv32i-mock-sram/{BUILD.bazel => fakeram7_256x32/BUILD} (100%) rename flow/designs/asap7/{riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel => riscv32i/BUILD} (100%) rename flow/designs/asap7/{riscv32i/BUILD.bazel => swerv_wrapper/BUILD} (100%) rename flow/designs/asap7/swerv_wrapper/lef/{BUILD.bazel => BUILD} (100%) rename flow/designs/asap7/swerv_wrapper/lib/{BUILD.bazel => BUILD} (100%) rename flow/designs/asap7/{swerv_wrapper/BUILD.bazel => uart/BUILD} (100%) rename flow/designs/{asap7/uart/BUILD.bazel => gf180/aes-hybrid/BUILD} (100%) rename flow/designs/gf180/{aes-hybrid/BUILD.bazel => aes/BUILD} (100%) rename flow/designs/gf180/{aes/BUILD.bazel => ibex/BUILD} (100%) rename flow/designs/gf180/{ibex/BUILD.bazel => jpeg/BUILD} (100%) rename flow/designs/gf180/{jpeg/BUILD.bazel => riscv32i/BUILD} (100%) rename flow/designs/gf180/{riscv32i/BUILD.bazel => uart-blocks/BUILD} (100%) rename flow/designs/gf180/uart-blocks/{BUILD.bazel => uart_rx/BUILD} (100%) rename flow/designs/{gf180/uart-blocks/uart_rx/BUILD.bazel => ihp-sg13g2/aes/BUILD} (100%) rename flow/designs/ihp-sg13g2/{aes/BUILD.bazel => gcd/BUILD} (100%) rename flow/designs/ihp-sg13g2/{gcd/BUILD.bazel => i2c-gpio-expander/BUILD} (100%) rename flow/designs/ihp-sg13g2/i2c-gpio-expander/{BUILD.bazel => I2cDeviceCtrl/BUILD} (100%) rename flow/designs/ihp-sg13g2/{i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel => ibex/BUILD} (100%) rename flow/designs/ihp-sg13g2/{ibex/BUILD.bazel => jpeg/BUILD} (100%) rename flow/designs/ihp-sg13g2/{jpeg/BUILD.bazel => riscv32i/BUILD} (100%) rename flow/designs/ihp-sg13g2/{riscv32i/BUILD.bazel => spi/BUILD} (100%) rename flow/designs/{ihp-sg13g2/spi/BUILD.bazel => nangate45/aes/BUILD} (100%) rename flow/designs/nangate45/{aes/BUILD.bazel => ariane133/BUILD} (100%) rename flow/designs/nangate45/{ariane133/BUILD.bazel => ariane136/BUILD} (100%) rename flow/designs/nangate45/{ariane136/BUILD.bazel => black_parrot/BUILD} (100%) rename flow/designs/nangate45/{black_parrot/BUILD.bazel => bp_be_top/BUILD} (100%) rename flow/designs/nangate45/{bp_be_top/BUILD.bazel => bp_fe_top/BUILD} (100%) rename flow/designs/nangate45/{bp_fe_top/BUILD.bazel => bp_multi_top/BUILD} (100%) rename flow/designs/nangate45/{bp_multi_top/BUILD.bazel => bp_quad/BUILD} (100%) rename flow/designs/nangate45/{bp_quad/BUILD.bazel => dynamic_node/BUILD} (100%) rename flow/designs/nangate45/{dynamic_node/BUILD.bazel => gcd/BUILD} (100%) rename flow/designs/nangate45/{gcd/BUILD.bazel => ibex/BUILD} (100%) rename flow/designs/nangate45/{ibex/BUILD.bazel => jpeg/BUILD} (100%) rename flow/designs/nangate45/{jpeg/BUILD.bazel => mempool_group/BUILD} (100%) rename flow/designs/nangate45/{mempool_group/BUILD.bazel => swerv/BUILD} (100%) rename flow/designs/nangate45/{swerv/BUILD.bazel => swerv_wrapper/BUILD} (100%) rename flow/designs/nangate45/{swerv_wrapper/BUILD.bazel => tinyRocket/BUILD} (100%) rename flow/designs/{nangate45/tinyRocket/BUILD.bazel => sky130hd/aes/BUILD} (100%) rename flow/designs/sky130hd/chameleon/{BUILD.bazel => BUILD} (100%) rename flow/designs/sky130hd/chameleon/gds/{BUILD.bazel => BUILD} (100%) rename flow/designs/sky130hd/chameleon/lef/{BUILD.bazel => BUILD} (100%) rename flow/designs/sky130hd/{aes/BUILD.bazel => gcd/BUILD} (100%) rename flow/designs/sky130hd/{gcd/BUILD.bazel => ibex/BUILD} (100%) rename flow/designs/sky130hd/{ibex/BUILD.bazel => jpeg/BUILD} (100%) rename flow/designs/sky130hd/{jpeg/BUILD.bazel => microwatt/BUILD} (100%) rename flow/designs/sky130hd/microwatt/gds/{BUILD.bazel => BUILD} (100%) rename flow/designs/sky130hd/microwatt/lef/{BUILD.bazel => BUILD} (100%) rename flow/designs/sky130hd/microwatt/lib/{BUILD.bazel => BUILD} (100%) rename flow/designs/sky130hd/{microwatt/BUILD.bazel => riscv32i/BUILD} (100%) rename flow/designs/{sky130hd/riscv32i/BUILD.bazel => sky130hs/aes/BUILD} (100%) rename flow/designs/sky130hs/{aes/BUILD.bazel => gcd/BUILD} (100%) rename flow/designs/sky130hs/{gcd/BUILD.bazel => ibex/BUILD} (100%) rename flow/designs/sky130hs/{ibex/BUILD.bazel => jpeg/BUILD} (100%) rename flow/designs/sky130hs/{jpeg/BUILD.bazel => riscv32i/BUILD} (100%) delete mode 100644 flow/designs/sky130hs/riscv32i/BUILD.bazel rename flow/designs/src/aes/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/ariane/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/ariane133/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/ariane136/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/black_parrot/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/bp_be_top/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/bp_fe_top/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/bp_multi_top/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/bp_quad/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/chameleon/AHB_sys_0/APB_sys_0/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/chameleon/AHB_sys_0/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/chameleon/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/chameleon/IPs/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/chameleon/IPs/apb2i2c/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/chameleon/acc/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/chameleon/ibex/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/chameleon/ibex/models/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/coyote/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/common/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/common/local/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/common/local/util/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cache_subsystem/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cache_subsystem/hpdcache/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cva6_mmu/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cvfpu/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cvfpu/src/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cvfpu/src/common_cells/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cvfpu/src/common_cells/include/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cvxif_example/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/cvxif_example/include/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/frontend/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/include/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/pmp/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/core/pmp/src/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/vendor/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/vendor/pulp-platform/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/vendor/pulp-platform/axi/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/vendor/pulp-platform/axi/src/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/vendor/pulp-platform/common_cells/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/dynamic_node/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/ethmac/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/fifo/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/gcd/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/ibex_sv/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/ibex_sv/syn/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/ibex_sv/syn/rtl/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/ibex_sv/vendor/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/ibex_sv/vendor/lowrisc_ip/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/jpeg/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/jpeg/include/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/axi/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/axi/src/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/cluster_interconnect/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/common_cells/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/common_cells/src/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/mempool/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/register_interface/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/register_interface/include/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/snitch/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/snitch/src/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/tech_cells_generic/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/tech_cells_generic/src/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/microwatt/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/microwatt/IPs/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mock-alu/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/mock-array/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/riscv32i/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/spi/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/swerv/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/tinyRocket/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/uart-no-param/{BUILD.bazel => BUILD} (100%) rename flow/designs/src/uart/{BUILD.bazel => BUILD} (100%) rename flow/util/{BUILD.bazel => BUILD} (100%) diff --git a/BUILD.bazel b/BUILD similarity index 100% rename from BUILD.bazel rename to BUILD diff --git a/MODULE.bazel b/MODULE.bazel index b7b2a70e71..4b2992fcc7 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -117,7 +117,7 @@ orfs_designs = use_repo_rule("@bazel-orfs//private:designs.bzl", "orfs_designs") orfs_designs( name = "orfs_designs", - designs_dir = "//flow/designs:BUILD.bazel", + designs_dir = "//flow/designs:BUILD", platforms = [ "asap7", "gf180", diff --git a/WORKSPACE.bazel b/WORKSPACE similarity index 100% rename from WORKSPACE.bazel rename to WORKSPACE diff --git a/flow/BUILD.bazel b/flow/BUILD similarity index 100% rename from flow/BUILD.bazel rename to flow/BUILD diff --git a/flow/designs/BUILD b/flow/designs/BUILD new file mode 100644 index 0000000000..0fe28bc544 --- /dev/null +++ b/flow/designs/BUILD @@ -0,0 +1 @@ +exports_files(["BUILD"]) diff --git a/flow/designs/BUILD.bazel b/flow/designs/BUILD.bazel deleted file mode 100644 index ed4e50dd79..0000000000 --- a/flow/designs/BUILD.bazel +++ /dev/null @@ -1 +0,0 @@ -exports_files(["BUILD.bazel"]) diff --git a/flow/designs/asap7/aes-block/BUILD.bazel b/flow/designs/asap7/aes-block/BUILD similarity index 100% rename from flow/designs/asap7/aes-block/BUILD.bazel rename to flow/designs/asap7/aes-block/BUILD diff --git a/flow/designs/asap7/aes-mbff/BUILD.bazel b/flow/designs/asap7/aes-mbff/BUILD similarity index 100% rename from flow/designs/asap7/aes-mbff/BUILD.bazel rename to flow/designs/asap7/aes-mbff/BUILD diff --git a/flow/designs/asap7/aes/BUILD.bazel b/flow/designs/asap7/aes/BUILD similarity index 100% rename from flow/designs/asap7/aes/BUILD.bazel rename to flow/designs/asap7/aes/BUILD diff --git a/flow/designs/asap7/aes_lvt/BUILD.bazel b/flow/designs/asap7/aes_lvt/BUILD similarity index 100% rename from flow/designs/asap7/aes_lvt/BUILD.bazel rename to flow/designs/asap7/aes_lvt/BUILD diff --git a/flow/designs/asap7/cva6/BUILD.bazel b/flow/designs/asap7/cva6/BUILD similarity index 100% rename from flow/designs/asap7/cva6/BUILD.bazel rename to flow/designs/asap7/cva6/BUILD diff --git a/flow/designs/asap7/ethmac/BUILD.bazel b/flow/designs/asap7/ethmac/BUILD similarity index 100% rename from flow/designs/asap7/ethmac/BUILD.bazel rename to flow/designs/asap7/ethmac/BUILD diff --git a/flow/designs/asap7/ethmac_lvt/BUILD.bazel b/flow/designs/asap7/ethmac_lvt/BUILD similarity index 100% rename from flow/designs/asap7/ethmac_lvt/BUILD.bazel rename to flow/designs/asap7/ethmac_lvt/BUILD diff --git a/flow/designs/asap7/gcd-ccs/BUILD.bazel b/flow/designs/asap7/gcd-ccs/BUILD similarity index 100% rename from flow/designs/asap7/gcd-ccs/BUILD.bazel rename to flow/designs/asap7/gcd-ccs/BUILD diff --git a/flow/designs/asap7/gcd/BUILD b/flow/designs/asap7/gcd/BUILD index 0736578fe6..527d6542e1 100644 --- a/flow/designs/asap7/gcd/BUILD +++ b/flow/designs/asap7/gcd/BUILD @@ -1,20 +1,3 @@ -load("@bazel-orfs//:openroad.bzl", "orfs_flow") +load("//flow/designs:design.bzl", "design") -orfs_flow( - name = "gcd", - arguments = { - # Faster builds - "SKIP_INCREMENTAL_REPAIR": "1", - "GPL_TIMING_DRIVEN": "0", - "SKIP_LAST_GASP": "1", - # Various - "DIE_AREA": "0 0 16.2 16.2", - "CORE_AREA": "1.08 1.08 15.12 15.12", - "PLACE_DENSITY": "0.35", - }, - sources = { - "RULES_JSON": [":rules-base.json"], - "SDC_FILE": [":constraint.sdc"], - }, - verilog_files = ["//flow/designs/src/gcd:verilog"], -) +design(config = "config.mk") diff --git a/flow/designs/asap7/gcd/BUILD.bazel b/flow/designs/asap7/ibex/BUILD similarity index 100% rename from flow/designs/asap7/gcd/BUILD.bazel rename to flow/designs/asap7/ibex/BUILD diff --git a/flow/designs/asap7/ibex/BUILD.bazel b/flow/designs/asap7/jpeg/BUILD similarity index 100% rename from flow/designs/asap7/ibex/BUILD.bazel rename to flow/designs/asap7/jpeg/BUILD diff --git a/flow/designs/asap7/jpeg/BUILD.bazel b/flow/designs/asap7/jpeg_lvt/BUILD similarity index 100% rename from flow/designs/asap7/jpeg/BUILD.bazel rename to flow/designs/asap7/jpeg_lvt/BUILD diff --git a/flow/designs/asap7/minimal/BUILD.bazel b/flow/designs/asap7/minimal/BUILD similarity index 100% rename from flow/designs/asap7/minimal/BUILD.bazel rename to flow/designs/asap7/minimal/BUILD diff --git a/flow/designs/asap7/jpeg_lvt/BUILD.bazel b/flow/designs/asap7/mock-alu/BUILD similarity index 100% rename from flow/designs/asap7/jpeg_lvt/BUILD.bazel rename to flow/designs/asap7/mock-alu/BUILD diff --git a/flow/designs/asap7/mock-alu/BUILD.bazel b/flow/designs/asap7/mock-cpu/BUILD similarity index 100% rename from flow/designs/asap7/mock-alu/BUILD.bazel rename to flow/designs/asap7/mock-cpu/BUILD diff --git a/flow/designs/asap7/mock-cpu/BUILD.bazel b/flow/designs/asap7/riscv32i-mock-sram/BUILD similarity index 100% rename from flow/designs/asap7/mock-cpu/BUILD.bazel rename to flow/designs/asap7/riscv32i-mock-sram/BUILD diff --git a/flow/designs/asap7/riscv32i-mock-sram/BUILD.bazel b/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD similarity index 100% rename from flow/designs/asap7/riscv32i-mock-sram/BUILD.bazel rename to flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD diff --git a/flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel b/flow/designs/asap7/riscv32i/BUILD similarity index 100% rename from flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel rename to flow/designs/asap7/riscv32i/BUILD diff --git a/flow/designs/asap7/riscv32i/BUILD.bazel b/flow/designs/asap7/swerv_wrapper/BUILD similarity index 100% rename from flow/designs/asap7/riscv32i/BUILD.bazel rename to flow/designs/asap7/swerv_wrapper/BUILD diff --git a/flow/designs/asap7/swerv_wrapper/lef/BUILD.bazel b/flow/designs/asap7/swerv_wrapper/lef/BUILD similarity index 100% rename from flow/designs/asap7/swerv_wrapper/lef/BUILD.bazel rename to flow/designs/asap7/swerv_wrapper/lef/BUILD diff --git a/flow/designs/asap7/swerv_wrapper/lib/BUILD.bazel b/flow/designs/asap7/swerv_wrapper/lib/BUILD similarity index 100% rename from flow/designs/asap7/swerv_wrapper/lib/BUILD.bazel rename to flow/designs/asap7/swerv_wrapper/lib/BUILD diff --git a/flow/designs/asap7/swerv_wrapper/BUILD.bazel b/flow/designs/asap7/uart/BUILD similarity index 100% rename from flow/designs/asap7/swerv_wrapper/BUILD.bazel rename to flow/designs/asap7/uart/BUILD diff --git a/flow/designs/design.bzl b/flow/designs/design.bzl index 9d60aadae0..ff48d681a2 100644 --- a/flow/designs/design.bzl +++ b/flow/designs/design.bzl @@ -1,4 +1,4 @@ -"""BUILD.bazel boilerplate for flow/designs/.""" +"""BUILD boilerplate for flow/designs/.""" load("@orfs_designs//:designs.bzl", "orfs_design") diff --git a/flow/designs/asap7/uart/BUILD.bazel b/flow/designs/gf180/aes-hybrid/BUILD similarity index 100% rename from flow/designs/asap7/uart/BUILD.bazel rename to flow/designs/gf180/aes-hybrid/BUILD diff --git a/flow/designs/gf180/aes-hybrid/BUILD.bazel b/flow/designs/gf180/aes/BUILD similarity index 100% rename from flow/designs/gf180/aes-hybrid/BUILD.bazel rename to flow/designs/gf180/aes/BUILD diff --git a/flow/designs/gf180/aes/BUILD.bazel b/flow/designs/gf180/ibex/BUILD similarity index 100% rename from flow/designs/gf180/aes/BUILD.bazel rename to flow/designs/gf180/ibex/BUILD diff --git a/flow/designs/gf180/ibex/BUILD.bazel b/flow/designs/gf180/jpeg/BUILD similarity index 100% rename from flow/designs/gf180/ibex/BUILD.bazel rename to flow/designs/gf180/jpeg/BUILD diff --git a/flow/designs/gf180/jpeg/BUILD.bazel b/flow/designs/gf180/riscv32i/BUILD similarity index 100% rename from flow/designs/gf180/jpeg/BUILD.bazel rename to flow/designs/gf180/riscv32i/BUILD diff --git a/flow/designs/gf180/riscv32i/BUILD.bazel b/flow/designs/gf180/uart-blocks/BUILD similarity index 100% rename from flow/designs/gf180/riscv32i/BUILD.bazel rename to flow/designs/gf180/uart-blocks/BUILD diff --git a/flow/designs/gf180/uart-blocks/BUILD.bazel b/flow/designs/gf180/uart-blocks/uart_rx/BUILD similarity index 100% rename from flow/designs/gf180/uart-blocks/BUILD.bazel rename to flow/designs/gf180/uart-blocks/uart_rx/BUILD diff --git a/flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel b/flow/designs/ihp-sg13g2/aes/BUILD similarity index 100% rename from flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel rename to flow/designs/ihp-sg13g2/aes/BUILD diff --git a/flow/designs/ihp-sg13g2/aes/BUILD.bazel b/flow/designs/ihp-sg13g2/gcd/BUILD similarity index 100% rename from flow/designs/ihp-sg13g2/aes/BUILD.bazel rename to flow/designs/ihp-sg13g2/gcd/BUILD diff --git a/flow/designs/ihp-sg13g2/gcd/BUILD.bazel b/flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD similarity index 100% rename from flow/designs/ihp-sg13g2/gcd/BUILD.bazel rename to flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel b/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD similarity index 100% rename from flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel rename to flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel b/flow/designs/ihp-sg13g2/ibex/BUILD similarity index 100% rename from flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel rename to flow/designs/ihp-sg13g2/ibex/BUILD diff --git a/flow/designs/ihp-sg13g2/ibex/BUILD.bazel b/flow/designs/ihp-sg13g2/jpeg/BUILD similarity index 100% rename from flow/designs/ihp-sg13g2/ibex/BUILD.bazel rename to flow/designs/ihp-sg13g2/jpeg/BUILD diff --git a/flow/designs/ihp-sg13g2/jpeg/BUILD.bazel b/flow/designs/ihp-sg13g2/riscv32i/BUILD similarity index 100% rename from flow/designs/ihp-sg13g2/jpeg/BUILD.bazel rename to flow/designs/ihp-sg13g2/riscv32i/BUILD diff --git a/flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel b/flow/designs/ihp-sg13g2/spi/BUILD similarity index 100% rename from flow/designs/ihp-sg13g2/riscv32i/BUILD.bazel rename to flow/designs/ihp-sg13g2/spi/BUILD diff --git a/flow/designs/ihp-sg13g2/spi/BUILD.bazel b/flow/designs/nangate45/aes/BUILD similarity index 100% rename from flow/designs/ihp-sg13g2/spi/BUILD.bazel rename to flow/designs/nangate45/aes/BUILD diff --git a/flow/designs/nangate45/aes/BUILD.bazel b/flow/designs/nangate45/ariane133/BUILD similarity index 100% rename from flow/designs/nangate45/aes/BUILD.bazel rename to flow/designs/nangate45/ariane133/BUILD diff --git a/flow/designs/nangate45/ariane133/BUILD.bazel b/flow/designs/nangate45/ariane136/BUILD similarity index 100% rename from flow/designs/nangate45/ariane133/BUILD.bazel rename to flow/designs/nangate45/ariane136/BUILD diff --git a/flow/designs/nangate45/ariane136/BUILD.bazel b/flow/designs/nangate45/black_parrot/BUILD similarity index 100% rename from flow/designs/nangate45/ariane136/BUILD.bazel rename to flow/designs/nangate45/black_parrot/BUILD diff --git a/flow/designs/nangate45/black_parrot/BUILD.bazel b/flow/designs/nangate45/bp_be_top/BUILD similarity index 100% rename from flow/designs/nangate45/black_parrot/BUILD.bazel rename to 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a/flow/designs/nangate45/dynamic_node/BUILD.bazel b/flow/designs/nangate45/gcd/BUILD similarity index 100% rename from flow/designs/nangate45/dynamic_node/BUILD.bazel rename to flow/designs/nangate45/gcd/BUILD diff --git a/flow/designs/nangate45/gcd/BUILD.bazel b/flow/designs/nangate45/ibex/BUILD similarity index 100% rename from flow/designs/nangate45/gcd/BUILD.bazel rename to flow/designs/nangate45/ibex/BUILD diff --git a/flow/designs/nangate45/ibex/BUILD.bazel b/flow/designs/nangate45/jpeg/BUILD similarity index 100% rename from flow/designs/nangate45/ibex/BUILD.bazel rename to flow/designs/nangate45/jpeg/BUILD diff --git a/flow/designs/nangate45/jpeg/BUILD.bazel b/flow/designs/nangate45/mempool_group/BUILD similarity index 100% rename from flow/designs/nangate45/jpeg/BUILD.bazel rename to flow/designs/nangate45/mempool_group/BUILD diff --git a/flow/designs/nangate45/mempool_group/BUILD.bazel b/flow/designs/nangate45/swerv/BUILD similarity index 100% rename from flow/designs/nangate45/mempool_group/BUILD.bazel rename to flow/designs/nangate45/swerv/BUILD diff --git a/flow/designs/nangate45/swerv/BUILD.bazel b/flow/designs/nangate45/swerv_wrapper/BUILD similarity index 100% rename from flow/designs/nangate45/swerv/BUILD.bazel rename to flow/designs/nangate45/swerv_wrapper/BUILD diff --git a/flow/designs/nangate45/swerv_wrapper/BUILD.bazel b/flow/designs/nangate45/tinyRocket/BUILD similarity index 100% rename from flow/designs/nangate45/swerv_wrapper/BUILD.bazel rename to flow/designs/nangate45/tinyRocket/BUILD diff --git a/flow/designs/nangate45/tinyRocket/BUILD.bazel b/flow/designs/sky130hd/aes/BUILD similarity index 100% rename from flow/designs/nangate45/tinyRocket/BUILD.bazel rename to flow/designs/sky130hd/aes/BUILD diff --git a/flow/designs/sky130hd/chameleon/BUILD.bazel b/flow/designs/sky130hd/chameleon/BUILD similarity index 100% rename from flow/designs/sky130hd/chameleon/BUILD.bazel rename to flow/designs/sky130hd/chameleon/BUILD diff --git a/flow/designs/sky130hd/chameleon/gds/BUILD.bazel b/flow/designs/sky130hd/chameleon/gds/BUILD similarity index 100% rename from flow/designs/sky130hd/chameleon/gds/BUILD.bazel rename to flow/designs/sky130hd/chameleon/gds/BUILD diff --git a/flow/designs/sky130hd/chameleon/lef/BUILD.bazel b/flow/designs/sky130hd/chameleon/lef/BUILD similarity index 100% rename from flow/designs/sky130hd/chameleon/lef/BUILD.bazel rename to flow/designs/sky130hd/chameleon/lef/BUILD diff --git a/flow/designs/sky130hd/aes/BUILD.bazel b/flow/designs/sky130hd/gcd/BUILD similarity index 100% rename from flow/designs/sky130hd/aes/BUILD.bazel rename to flow/designs/sky130hd/gcd/BUILD diff --git a/flow/designs/sky130hd/gcd/BUILD.bazel b/flow/designs/sky130hd/ibex/BUILD similarity index 100% rename from flow/designs/sky130hd/gcd/BUILD.bazel rename to flow/designs/sky130hd/ibex/BUILD diff --git a/flow/designs/sky130hd/ibex/BUILD.bazel b/flow/designs/sky130hd/jpeg/BUILD similarity index 100% rename from flow/designs/sky130hd/ibex/BUILD.bazel rename to flow/designs/sky130hd/jpeg/BUILD diff --git a/flow/designs/sky130hd/jpeg/BUILD.bazel b/flow/designs/sky130hd/microwatt/BUILD similarity index 100% rename from flow/designs/sky130hd/jpeg/BUILD.bazel rename to flow/designs/sky130hd/microwatt/BUILD diff --git a/flow/designs/sky130hd/microwatt/gds/BUILD.bazel b/flow/designs/sky130hd/microwatt/gds/BUILD similarity index 100% rename from flow/designs/sky130hd/microwatt/gds/BUILD.bazel rename to flow/designs/sky130hd/microwatt/gds/BUILD diff --git a/flow/designs/sky130hd/microwatt/lef/BUILD.bazel b/flow/designs/sky130hd/microwatt/lef/BUILD similarity index 100% rename from flow/designs/sky130hd/microwatt/lef/BUILD.bazel rename to flow/designs/sky130hd/microwatt/lef/BUILD diff --git a/flow/designs/sky130hd/microwatt/lib/BUILD.bazel b/flow/designs/sky130hd/microwatt/lib/BUILD similarity index 100% rename from flow/designs/sky130hd/microwatt/lib/BUILD.bazel rename to flow/designs/sky130hd/microwatt/lib/BUILD diff --git a/flow/designs/sky130hd/microwatt/BUILD.bazel b/flow/designs/sky130hd/riscv32i/BUILD similarity index 100% rename from flow/designs/sky130hd/microwatt/BUILD.bazel rename to flow/designs/sky130hd/riscv32i/BUILD diff --git a/flow/designs/sky130hd/riscv32i/BUILD.bazel b/flow/designs/sky130hs/aes/BUILD similarity index 100% rename from flow/designs/sky130hd/riscv32i/BUILD.bazel rename to flow/designs/sky130hs/aes/BUILD diff --git a/flow/designs/sky130hs/aes/BUILD.bazel b/flow/designs/sky130hs/gcd/BUILD similarity index 100% rename from flow/designs/sky130hs/aes/BUILD.bazel rename to flow/designs/sky130hs/gcd/BUILD diff --git a/flow/designs/sky130hs/gcd/BUILD.bazel b/flow/designs/sky130hs/ibex/BUILD similarity index 100% rename from flow/designs/sky130hs/gcd/BUILD.bazel rename to flow/designs/sky130hs/ibex/BUILD diff --git a/flow/designs/sky130hs/ibex/BUILD.bazel b/flow/designs/sky130hs/jpeg/BUILD similarity index 100% rename from flow/designs/sky130hs/ibex/BUILD.bazel rename to flow/designs/sky130hs/jpeg/BUILD diff --git a/flow/designs/sky130hs/jpeg/BUILD.bazel b/flow/designs/sky130hs/riscv32i/BUILD similarity index 100% rename from flow/designs/sky130hs/jpeg/BUILD.bazel rename to flow/designs/sky130hs/riscv32i/BUILD diff --git a/flow/designs/sky130hs/riscv32i/BUILD.bazel b/flow/designs/sky130hs/riscv32i/BUILD.bazel deleted file mode 100644 index 527d6542e1..0000000000 --- a/flow/designs/sky130hs/riscv32i/BUILD.bazel +++ /dev/null @@ -1,3 +0,0 @@ -load("//flow/designs:design.bzl", "design") - -design(config = "config.mk") diff --git a/flow/designs/src/aes/BUILD.bazel b/flow/designs/src/aes/BUILD similarity index 100% rename from flow/designs/src/aes/BUILD.bazel rename to flow/designs/src/aes/BUILD diff --git a/flow/designs/src/ariane/BUILD.bazel b/flow/designs/src/ariane/BUILD similarity index 100% rename from flow/designs/src/ariane/BUILD.bazel rename to flow/designs/src/ariane/BUILD diff --git a/flow/designs/src/ariane133/BUILD.bazel b/flow/designs/src/ariane133/BUILD similarity index 100% rename from flow/designs/src/ariane133/BUILD.bazel rename to flow/designs/src/ariane133/BUILD diff --git a/flow/designs/src/ariane136/BUILD.bazel b/flow/designs/src/ariane136/BUILD similarity index 100% rename from flow/designs/src/ariane136/BUILD.bazel rename to flow/designs/src/ariane136/BUILD diff --git a/flow/designs/src/black_parrot/BUILD.bazel b/flow/designs/src/black_parrot/BUILD similarity index 100% rename from flow/designs/src/black_parrot/BUILD.bazel rename to flow/designs/src/black_parrot/BUILD diff --git a/flow/designs/src/bp_be_top/BUILD.bazel b/flow/designs/src/bp_be_top/BUILD similarity index 100% rename from flow/designs/src/bp_be_top/BUILD.bazel rename to flow/designs/src/bp_be_top/BUILD diff --git a/flow/designs/src/bp_fe_top/BUILD.bazel b/flow/designs/src/bp_fe_top/BUILD similarity index 100% rename from flow/designs/src/bp_fe_top/BUILD.bazel rename to flow/designs/src/bp_fe_top/BUILD diff --git a/flow/designs/src/bp_multi_top/BUILD.bazel b/flow/designs/src/bp_multi_top/BUILD similarity index 100% rename from flow/designs/src/bp_multi_top/BUILD.bazel rename to flow/designs/src/bp_multi_top/BUILD diff --git a/flow/designs/src/bp_quad/BUILD.bazel b/flow/designs/src/bp_quad/BUILD similarity index 100% rename from flow/designs/src/bp_quad/BUILD.bazel rename to flow/designs/src/bp_quad/BUILD diff --git a/flow/designs/src/chameleon/AHB_sys_0/APB_sys_0/BUILD.bazel b/flow/designs/src/chameleon/AHB_sys_0/APB_sys_0/BUILD similarity index 100% rename from flow/designs/src/chameleon/AHB_sys_0/APB_sys_0/BUILD.bazel rename to flow/designs/src/chameleon/AHB_sys_0/APB_sys_0/BUILD diff --git a/flow/designs/src/chameleon/AHB_sys_0/BUILD.bazel b/flow/designs/src/chameleon/AHB_sys_0/BUILD similarity index 100% rename from flow/designs/src/chameleon/AHB_sys_0/BUILD.bazel rename to flow/designs/src/chameleon/AHB_sys_0/BUILD diff --git a/flow/designs/src/chameleon/BUILD.bazel b/flow/designs/src/chameleon/BUILD similarity index 100% rename from flow/designs/src/chameleon/BUILD.bazel rename to flow/designs/src/chameleon/BUILD diff --git a/flow/designs/src/chameleon/IPs/BUILD.bazel b/flow/designs/src/chameleon/IPs/BUILD similarity index 100% rename from flow/designs/src/chameleon/IPs/BUILD.bazel rename to flow/designs/src/chameleon/IPs/BUILD diff --git a/flow/designs/src/chameleon/IPs/apb2i2c/BUILD.bazel b/flow/designs/src/chameleon/IPs/apb2i2c/BUILD similarity index 100% rename from flow/designs/src/chameleon/IPs/apb2i2c/BUILD.bazel rename to flow/designs/src/chameleon/IPs/apb2i2c/BUILD diff --git a/flow/designs/src/chameleon/acc/BUILD.bazel b/flow/designs/src/chameleon/acc/BUILD similarity index 100% rename from flow/designs/src/chameleon/acc/BUILD.bazel rename to flow/designs/src/chameleon/acc/BUILD diff --git a/flow/designs/src/chameleon/ibex/BUILD.bazel b/flow/designs/src/chameleon/ibex/BUILD similarity index 100% rename from flow/designs/src/chameleon/ibex/BUILD.bazel rename to flow/designs/src/chameleon/ibex/BUILD diff --git a/flow/designs/src/chameleon/ibex/models/BUILD.bazel b/flow/designs/src/chameleon/ibex/models/BUILD similarity index 100% rename from flow/designs/src/chameleon/ibex/models/BUILD.bazel rename to flow/designs/src/chameleon/ibex/models/BUILD diff --git a/flow/designs/src/coyote/BUILD.bazel b/flow/designs/src/coyote/BUILD similarity index 100% rename from flow/designs/src/coyote/BUILD.bazel rename to flow/designs/src/coyote/BUILD diff --git a/flow/designs/src/cva6/BUILD.bazel b/flow/designs/src/cva6/BUILD similarity index 100% rename from flow/designs/src/cva6/BUILD.bazel rename to flow/designs/src/cva6/BUILD diff --git a/flow/designs/src/cva6/common/BUILD.bazel b/flow/designs/src/cva6/common/BUILD similarity index 100% rename from flow/designs/src/cva6/common/BUILD.bazel rename to flow/designs/src/cva6/common/BUILD diff --git a/flow/designs/src/cva6/common/local/BUILD.bazel b/flow/designs/src/cva6/common/local/BUILD similarity index 100% rename from flow/designs/src/cva6/common/local/BUILD.bazel rename to flow/designs/src/cva6/common/local/BUILD diff --git a/flow/designs/src/cva6/common/local/util/BUILD.bazel b/flow/designs/src/cva6/common/local/util/BUILD similarity index 100% rename from flow/designs/src/cva6/common/local/util/BUILD.bazel rename to flow/designs/src/cva6/common/local/util/BUILD diff --git a/flow/designs/src/cva6/core/BUILD.bazel b/flow/designs/src/cva6/core/BUILD similarity index 100% rename from flow/designs/src/cva6/core/BUILD.bazel rename to flow/designs/src/cva6/core/BUILD diff --git a/flow/designs/src/cva6/core/cache_subsystem/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cache_subsystem/BUILD.bazel rename to flow/designs/src/cva6/core/cache_subsystem/BUILD diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cache_subsystem/hpdcache/BUILD.bazel rename to flow/designs/src/cva6/core/cache_subsystem/hpdcache/BUILD diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/BUILD.bazel rename to flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/BUILD diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/BUILD.bazel rename to flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/include/BUILD diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/BUILD.bazel rename to flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/BUILD diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/BUILD.bazel rename to flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/BUILD diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/BUILD.bazel rename to flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/BUILD diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/BUILD.bazel rename to flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/BUILD diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/BUILD.bazel rename to flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/BUILD diff --git a/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/BUILD.bazel b/flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/BUILD.bazel rename to flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/utils/BUILD diff --git a/flow/designs/src/cva6/core/cva6_mmu/BUILD.bazel b/flow/designs/src/cva6/core/cva6_mmu/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cva6_mmu/BUILD.bazel rename to flow/designs/src/cva6/core/cva6_mmu/BUILD diff --git a/flow/designs/src/cva6/core/cvfpu/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cvfpu/BUILD.bazel rename to flow/designs/src/cva6/core/cvfpu/BUILD diff --git a/flow/designs/src/cva6/core/cvfpu/src/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cvfpu/src/BUILD.bazel rename to flow/designs/src/cva6/core/cvfpu/src/BUILD diff --git a/flow/designs/src/cva6/core/cvfpu/src/common_cells/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/common_cells/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cvfpu/src/common_cells/BUILD.bazel rename to flow/designs/src/cva6/core/cvfpu/src/common_cells/BUILD diff --git a/flow/designs/src/cva6/core/cvfpu/src/common_cells/include/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/common_cells/include/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cvfpu/src/common_cells/include/BUILD.bazel rename to flow/designs/src/cva6/core/cvfpu/src/common_cells/include/BUILD diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/BUILD.bazel rename to flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/BUILD diff --git a/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/BUILD.bazel b/flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/BUILD.bazel rename to flow/designs/src/cva6/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/BUILD diff --git a/flow/designs/src/cva6/core/cvxif_example/BUILD.bazel b/flow/designs/src/cva6/core/cvxif_example/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cvxif_example/BUILD.bazel rename to flow/designs/src/cva6/core/cvxif_example/BUILD diff --git a/flow/designs/src/cva6/core/cvxif_example/include/BUILD.bazel b/flow/designs/src/cva6/core/cvxif_example/include/BUILD similarity index 100% rename from flow/designs/src/cva6/core/cvxif_example/include/BUILD.bazel rename to flow/designs/src/cva6/core/cvxif_example/include/BUILD diff --git a/flow/designs/src/cva6/core/frontend/BUILD.bazel b/flow/designs/src/cva6/core/frontend/BUILD similarity index 100% rename from flow/designs/src/cva6/core/frontend/BUILD.bazel rename to flow/designs/src/cva6/core/frontend/BUILD diff --git a/flow/designs/src/cva6/core/include/BUILD.bazel b/flow/designs/src/cva6/core/include/BUILD similarity index 100% rename from flow/designs/src/cva6/core/include/BUILD.bazel rename to flow/designs/src/cva6/core/include/BUILD diff --git a/flow/designs/src/cva6/core/pmp/BUILD.bazel b/flow/designs/src/cva6/core/pmp/BUILD similarity index 100% rename from flow/designs/src/cva6/core/pmp/BUILD.bazel rename to flow/designs/src/cva6/core/pmp/BUILD diff --git a/flow/designs/src/cva6/core/pmp/src/BUILD.bazel b/flow/designs/src/cva6/core/pmp/src/BUILD similarity index 100% rename from flow/designs/src/cva6/core/pmp/src/BUILD.bazel rename to flow/designs/src/cva6/core/pmp/src/BUILD diff --git a/flow/designs/src/cva6/vendor/BUILD.bazel b/flow/designs/src/cva6/vendor/BUILD similarity index 100% rename from flow/designs/src/cva6/vendor/BUILD.bazel rename to flow/designs/src/cva6/vendor/BUILD diff --git a/flow/designs/src/cva6/vendor/pulp-platform/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/BUILD similarity index 100% rename from flow/designs/src/cva6/vendor/pulp-platform/BUILD.bazel rename to flow/designs/src/cva6/vendor/pulp-platform/BUILD diff --git a/flow/designs/src/cva6/vendor/pulp-platform/axi/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/axi/BUILD similarity index 100% rename from flow/designs/src/cva6/vendor/pulp-platform/axi/BUILD.bazel rename to flow/designs/src/cva6/vendor/pulp-platform/axi/BUILD diff --git a/flow/designs/src/cva6/vendor/pulp-platform/axi/src/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/axi/src/BUILD similarity index 100% rename from flow/designs/src/cva6/vendor/pulp-platform/axi/src/BUILD.bazel rename to flow/designs/src/cva6/vendor/pulp-platform/axi/src/BUILD diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/BUILD similarity index 100% rename from flow/designs/src/cva6/vendor/pulp-platform/common_cells/BUILD.bazel rename to flow/designs/src/cva6/vendor/pulp-platform/common_cells/BUILD diff --git a/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/BUILD similarity index 100% rename from flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/BUILD.bazel rename to flow/designs/src/cva6/vendor/pulp-platform/common_cells/src/BUILD diff --git a/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/BUILD similarity index 100% rename from flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/BUILD.bazel rename to flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/BUILD diff --git a/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/BUILD similarity index 100% rename from flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/BUILD.bazel rename to flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/BUILD diff --git a/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/BUILD.bazel b/flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/BUILD similarity index 100% rename from flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/BUILD.bazel rename to flow/designs/src/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/BUILD diff --git a/flow/designs/src/dynamic_node/BUILD.bazel b/flow/designs/src/dynamic_node/BUILD similarity index 100% rename from flow/designs/src/dynamic_node/BUILD.bazel rename to flow/designs/src/dynamic_node/BUILD diff --git a/flow/designs/src/ethmac/BUILD.bazel b/flow/designs/src/ethmac/BUILD similarity index 100% rename from flow/designs/src/ethmac/BUILD.bazel rename to flow/designs/src/ethmac/BUILD diff --git a/flow/designs/src/fifo/BUILD.bazel b/flow/designs/src/fifo/BUILD similarity index 100% rename from flow/designs/src/fifo/BUILD.bazel rename to flow/designs/src/fifo/BUILD diff --git a/flow/designs/src/gcd/BUILD.bazel b/flow/designs/src/gcd/BUILD similarity index 100% rename from flow/designs/src/gcd/BUILD.bazel rename to flow/designs/src/gcd/BUILD diff --git a/flow/designs/src/ibex_sv/BUILD.bazel b/flow/designs/src/ibex_sv/BUILD similarity index 100% rename from flow/designs/src/ibex_sv/BUILD.bazel rename to flow/designs/src/ibex_sv/BUILD diff --git a/flow/designs/src/ibex_sv/syn/BUILD.bazel b/flow/designs/src/ibex_sv/syn/BUILD similarity index 100% rename from flow/designs/src/ibex_sv/syn/BUILD.bazel rename to flow/designs/src/ibex_sv/syn/BUILD diff --git a/flow/designs/src/ibex_sv/syn/rtl/BUILD.bazel b/flow/designs/src/ibex_sv/syn/rtl/BUILD similarity index 100% rename from flow/designs/src/ibex_sv/syn/rtl/BUILD.bazel rename to flow/designs/src/ibex_sv/syn/rtl/BUILD diff --git a/flow/designs/src/ibex_sv/vendor/BUILD.bazel b/flow/designs/src/ibex_sv/vendor/BUILD similarity index 100% rename from flow/designs/src/ibex_sv/vendor/BUILD.bazel rename to flow/designs/src/ibex_sv/vendor/BUILD diff --git a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/BUILD.bazel b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/BUILD similarity index 100% rename from flow/designs/src/ibex_sv/vendor/lowrisc_ip/BUILD.bazel rename to flow/designs/src/ibex_sv/vendor/lowrisc_ip/BUILD diff --git a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/BUILD.bazel b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/BUILD similarity index 100% rename from flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/BUILD.bazel rename to flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/BUILD diff --git a/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/BUILD.bazel b/flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/BUILD similarity index 100% rename from flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/BUILD.bazel rename to flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/BUILD diff --git a/flow/designs/src/jpeg/BUILD.bazel b/flow/designs/src/jpeg/BUILD similarity index 100% rename from flow/designs/src/jpeg/BUILD.bazel rename to flow/designs/src/jpeg/BUILD diff --git a/flow/designs/src/jpeg/include/BUILD.bazel b/flow/designs/src/jpeg/include/BUILD similarity index 100% rename from flow/designs/src/jpeg/include/BUILD.bazel rename to flow/designs/src/jpeg/include/BUILD diff --git a/flow/designs/src/mempool_group/BUILD.bazel b/flow/designs/src/mempool_group/BUILD similarity index 100% rename from flow/designs/src/mempool_group/BUILD.bazel rename to flow/designs/src/mempool_group/BUILD diff --git a/flow/designs/src/mempool_group/rtl/BUILD.bazel b/flow/designs/src/mempool_group/rtl/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/BUILD diff --git a/flow/designs/src/mempool_group/rtl/axi/BUILD.bazel b/flow/designs/src/mempool_group/rtl/axi/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/axi/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/axi/BUILD diff --git a/flow/designs/src/mempool_group/rtl/axi/src/BUILD.bazel b/flow/designs/src/mempool_group/rtl/axi/src/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/axi/src/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/axi/src/BUILD diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/BUILD.bazel b/flow/designs/src/mempool_group/rtl/cluster_interconnect/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/cluster_interconnect/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/cluster_interconnect/BUILD diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/BUILD.bazel b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/BUILD diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/BUILD.bazel b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/tcdm_interconnect/BUILD diff --git a/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/BUILD.bazel b/flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/cluster_interconnect/rtl/variable_latency_interconnect/BUILD diff --git a/flow/designs/src/mempool_group/rtl/common_cells/BUILD.bazel b/flow/designs/src/mempool_group/rtl/common_cells/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/common_cells/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/common_cells/BUILD diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/BUILD.bazel b/flow/designs/src/mempool_group/rtl/common_cells/src/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/common_cells/src/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/common_cells/src/BUILD diff --git a/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/BUILD.bazel b/flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/common_cells/src/deprecated/BUILD diff --git a/flow/designs/src/mempool_group/rtl/mempool/BUILD.bazel b/flow/designs/src/mempool_group/rtl/mempool/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/mempool/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/mempool/BUILD diff --git a/flow/designs/src/mempool_group/rtl/register_interface/BUILD.bazel b/flow/designs/src/mempool_group/rtl/register_interface/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/register_interface/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/register_interface/BUILD diff --git a/flow/designs/src/mempool_group/rtl/register_interface/include/BUILD.bazel b/flow/designs/src/mempool_group/rtl/register_interface/include/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/register_interface/include/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/register_interface/include/BUILD diff --git a/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/BUILD.bazel b/flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/register_interface/include/register_interface/BUILD diff --git a/flow/designs/src/mempool_group/rtl/snitch/BUILD.bazel b/flow/designs/src/mempool_group/rtl/snitch/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/snitch/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/snitch/BUILD diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/BUILD.bazel b/flow/designs/src/mempool_group/rtl/snitch/src/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/snitch/src/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/snitch/src/BUILD diff --git a/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/BUILD.bazel b/flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/snitch/src/snitch_icache/BUILD diff --git a/flow/designs/src/mempool_group/rtl/tech_cells_generic/BUILD.bazel b/flow/designs/src/mempool_group/rtl/tech_cells_generic/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/tech_cells_generic/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/tech_cells_generic/BUILD diff --git a/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/BUILD.bazel b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/tech_cells_generic/src/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/tech_cells_generic/src/BUILD diff --git a/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/BUILD.bazel b/flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/BUILD similarity index 100% rename from flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/BUILD.bazel rename to flow/designs/src/mempool_group/rtl/tech_cells_generic/src/rtl/BUILD diff --git a/flow/designs/src/microwatt/BUILD.bazel b/flow/designs/src/microwatt/BUILD similarity index 100% rename from flow/designs/src/microwatt/BUILD.bazel rename to flow/designs/src/microwatt/BUILD diff --git a/flow/designs/src/microwatt/IPs/BUILD.bazel b/flow/designs/src/microwatt/IPs/BUILD similarity index 100% rename from flow/designs/src/microwatt/IPs/BUILD.bazel rename to flow/designs/src/microwatt/IPs/BUILD diff --git a/flow/designs/src/mock-alu/BUILD.bazel b/flow/designs/src/mock-alu/BUILD similarity index 100% rename from flow/designs/src/mock-alu/BUILD.bazel rename to flow/designs/src/mock-alu/BUILD diff --git a/flow/designs/src/mock-array/BUILD.bazel b/flow/designs/src/mock-array/BUILD similarity index 100% rename from flow/designs/src/mock-array/BUILD.bazel rename to flow/designs/src/mock-array/BUILD diff --git a/flow/designs/src/riscv32i/BUILD.bazel b/flow/designs/src/riscv32i/BUILD similarity index 100% rename from flow/designs/src/riscv32i/BUILD.bazel rename to flow/designs/src/riscv32i/BUILD diff --git a/flow/designs/src/spi/BUILD.bazel b/flow/designs/src/spi/BUILD similarity index 100% rename from flow/designs/src/spi/BUILD.bazel rename to flow/designs/src/spi/BUILD diff --git a/flow/designs/src/swerv/BUILD.bazel b/flow/designs/src/swerv/BUILD similarity index 100% rename from flow/designs/src/swerv/BUILD.bazel rename to flow/designs/src/swerv/BUILD diff --git a/flow/designs/src/tinyRocket/BUILD.bazel b/flow/designs/src/tinyRocket/BUILD similarity index 100% rename from flow/designs/src/tinyRocket/BUILD.bazel rename to flow/designs/src/tinyRocket/BUILD diff --git a/flow/designs/src/uart-no-param/BUILD.bazel b/flow/designs/src/uart-no-param/BUILD similarity index 100% rename from flow/designs/src/uart-no-param/BUILD.bazel rename to flow/designs/src/uart-no-param/BUILD diff --git a/flow/designs/src/uart/BUILD.bazel b/flow/designs/src/uart/BUILD similarity index 100% rename from flow/designs/src/uart/BUILD.bazel rename to flow/designs/src/uart/BUILD diff --git a/flow/util/BUILD.bazel b/flow/util/BUILD similarity index 100% rename from flow/util/BUILD.bazel rename to flow/util/BUILD From 980cc062f0e255e92df2d5ff2f2cb5f83a403b13 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 11 May 2026 13:10:40 +0200 Subject: [PATCH 24/28] bazel: add local_arguments= to orfs_design() for make-only helpers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some config.mk files declare exported helper variables (notably VERILOG_FILES_BLACKBOX in microwatt and chameleon) that are used only for $(VAR) expansion within the same config.mk and are never read by ORFS or by any user-supplied .tcl/.mk. They surfaced in bazel-orfs's parsed sources/arguments and tripped the variables.yaml validator. Patch 0002 adds local_arguments= to orfs_design(); listed vars are popped from both arguments and sources before orfs_flow() is called, so they neither get validated against variables.yaml nor leak into the per-stage environment. design() (flow/designs/design.bzl) forwards the kwarg. microwatt and chameleon now declare VERILOG_FILES_BLACKBOX in local_arguments. VERILOG_FILES_BLACKBOX is removed from variables.yaml (it was registered there only to silence the validator) and the generated variables.json / FlowVariables.md are regenerated. Drive-by: * add bazel/BUILD so //bazel:0001-...patch resolves (the patch label was referenced from MODULE.bazel but had no package definition). * move bazel-orfs.md under flow/ alongside the bazel rules it documents; update the pointer in MODULE.bazel. Signed-off-by: Øyvind Harboe --- MODULE.bazel | 7 +++- ...-local_arguments-to-drop-helper-vars.patch | 42 +++++++++++++++++++ bazel/BUILD | 1 + docs/user/FlowVariables.md | 2 - bazel-orfs.md => flow/bazel-orfs.md | 0 flow/designs/design.bzl | 12 +++++- flow/designs/sky130hd/chameleon/BUILD | 15 +++++-- flow/designs/sky130hd/microwatt/BUILD | 5 ++- flow/scripts/variables.json | 6 --- flow/scripts/variables.yaml | 8 ---- 10 files changed, 73 insertions(+), 25 deletions(-) create mode 100644 bazel/0002-orfs_design-add-local_arguments-to-drop-helper-vars.patch create mode 100644 bazel/BUILD rename bazel-orfs.md => flow/bazel-orfs.md (100%) diff --git a/MODULE.bazel b/MODULE.bazel index 4b2992fcc7..33965e2714 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -45,7 +45,10 @@ BAZEL_ORFS_REMOTE = "https://github.com/The-OpenROAD-Project/bazel-orfs.git" git_override( module_name = "bazel-orfs", commit = BAZEL_ORFS_COMMIT, - patches = ["//bazel:0001-orfs_design-accept-config-mk-explicitly-drop-exports.patch"], + patches = [ + "//bazel:0001-orfs_design-accept-config-mk-explicitly-drop-exports.patch", + "//bazel:0002-orfs_design-add-local_arguments-to-drop-helper-vars.patch", + ], patch_strip = 1, remote = BAZEL_ORFS_REMOTE, ) @@ -112,7 +115,7 @@ use_repo(orfs, "gnumake") use_repo(orfs, "orfs_variable_metadata") # Auto-generate orfs_flow() targets from config.mk files. -# See bazel-orfs.md for usage. +# See flow/bazel-orfs.md for usage. orfs_designs = use_repo_rule("@bazel-orfs//private:designs.bzl", "orfs_designs") orfs_designs( diff --git a/bazel/0002-orfs_design-add-local_arguments-to-drop-helper-vars.patch b/bazel/0002-orfs_design-add-local_arguments-to-drop-helper-vars.patch new file mode 100644 index 0000000000..83811d1c3c --- /dev/null +++ b/bazel/0002-orfs_design-add-local_arguments-to-drop-helper-vars.patch @@ -0,0 +1,42 @@ +diff --git a/private/orfs_design.bzl b/private/orfs_design.bzl +--- a/private/orfs_design.bzl ++++ b/private/orfs_design.bzl +@@ -47,7 +47,7 @@ + result[var] = converted + return result + +-def orfs_design(name = None, config = "config.mk", platform = None, design = None, designs = None, mock_openroad = None, mock_yosys = None, user_arguments = []): # buildifier: disable=unused-variable ++def orfs_design(name = None, config = "config.mk", platform = None, design = None, designs = None, mock_openroad = None, mock_yosys = None, user_arguments = [], local_arguments = []): # buildifier: disable=unused-variable + """Create orfs_flow() targets for a design based on its parsed config.mk. + + Usage: +@@ -79,6 +79,12 @@ + Routed through orfs_flow(user_arguments=...) to bypass the + variables.yaml validator instead of being checked as known + ORFS arguments. ++ local_arguments: List of variable names that are only used for ++ $(VAR) expansion within the same config.mk and are not read ++ by ORFS or by any user .tcl/.mk (e.g. VERILOG_FILES_BLACKBOX, ++ which appears verbatim inside VERILOG_FILES). These are ++ dropped entirely before orfs_flow() is invoked — neither ++ validated against variables.yaml nor exposed as env vars. + """ + if designs == None: + fail("orfs_design() requires designs: load orfs_design from @orfs_designs//:designs.bzl") +@@ -172,6 +178,16 @@ + # Real flow — uses Docker image with real OpenROAD/Yosys + arguments = dict(config["arguments"]) + ++ # Drop caller-flagged local helper vars used only via $(VAR) ++ # expansion within the same config.mk (e.g. VERILOG_FILES_BLACKBOX). ++ # They must not reach orfs_flow — they would either fail validation ++ # or be exposed as noise env vars. The config.mk parser may classify ++ # such helpers as either arguments or sources (e.g. when they expand ++ # to file globs), so drop from both. ++ for var in local_arguments: ++ arguments.pop(var, None) ++ sources.pop(var, None) ++ + # Move caller-flagged design-specific knobs out of arguments and into + # user_arguments so they bypass the variables.yaml validator. + user_args = {} diff --git a/bazel/BUILD b/bazel/BUILD new file mode 100644 index 0000000000..d518110449 --- /dev/null +++ b/bazel/BUILD @@ -0,0 +1 @@ +exports_files(glob(["*.patch"])) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 11fd392985..80d3073bc5 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -324,7 +324,6 @@ configuration file. | USE_NEGOTIATION| Enable using negotiation legalizer for detailed placement.| 0| | VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| | | VERILOG_FILES| The path to the design Verilog/SystemVerilog files providing a description of modules.| | -| VERILOG_FILES_BLACKBOX| Verilog files (typically `IPs/*.v`) that are appended to VERILOG_FILES in hierarchical designs and treated as blackbox modules by yosys. Only used by config.mk; ORFS doesn't read it as an env var.| | | VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | | VERILOG_TOP_PARAMS| Apply toplevel params (if exist). Passed in as a list of key value pairs in tcl syntax; separated by spaces: PARAM1 VALUE1 PARAM2 VALUE2| | | VIA_IN_PIN_MAX_LAYER| Passed as -via_in_pin_top_layer to pin_access and detailed_route.| | @@ -377,7 +376,6 @@ configuration file. - [UNSET_ABC9_BOX_CELLS](#UNSET_ABC9_BOX_CELLS) - [VERILOG_DEFINES](#VERILOG_DEFINES) - [VERILOG_FILES](#VERILOG_FILES) -- [VERILOG_FILES_BLACKBOX](#VERILOG_FILES_BLACKBOX) - [VERILOG_INCLUDE_DIRS](#VERILOG_INCLUDE_DIRS) - [VERILOG_TOP_PARAMS](#VERILOG_TOP_PARAMS) - [YOSYS_FLAGS](#YOSYS_FLAGS) diff --git a/bazel-orfs.md b/flow/bazel-orfs.md similarity index 100% rename from bazel-orfs.md rename to flow/bazel-orfs.md diff --git a/flow/designs/design.bzl b/flow/designs/design.bzl index ff48d681a2..0ea8d149f7 100644 --- a/flow/designs/design.bzl +++ b/flow/designs/design.bzl @@ -13,7 +13,7 @@ _GROUPS = { "gds": ["gds", "gds.gz"], } -def design(config = "config.mk", user_arguments = []): +def design(config = "config.mk", user_arguments = [], local_arguments = []): """Standard BUILD body for flow/designs///. Args: @@ -21,8 +21,16 @@ def design(config = "config.mk", user_arguments = []): user_arguments: see orfs_design — list of config.mk var names that are project-specific (read by the design's own .tcl/.mk, not by ORFS) and should bypass the variables.yaml validator. + local_arguments: see orfs_design — list of config.mk var names that + are pure make-only helpers (used only via $(VAR) expansion + within the same config.mk, never read by ORFS or by user + .tcl/.mk). Dropped entirely before orfs_flow() is invoked. """ - orfs_design(config = config, user_arguments = user_arguments) + orfs_design( + config = config, + user_arguments = user_arguments, + local_arguments = local_arguments, + ) def files(group, extra_srcs = None): """Named filegroup over conventional extensions.""" diff --git a/flow/designs/sky130hd/chameleon/BUILD b/flow/designs/sky130hd/chameleon/BUILD index 9d75a8d180..414ad64d62 100644 --- a/flow/designs/sky130hd/chameleon/BUILD +++ b/flow/designs/sky130hd/chameleon/BUILD @@ -3,7 +3,14 @@ load("//flow/designs:design.bzl", "design") # FP_PDN_RAIL_{OFFSET,WIDTH} are read by chameleon's own pdn.cfg, not # by ORFS itself — route them through user_arguments so the validator # doesn't reject them as unknown ORFS variables. -design(config = "config.mk", user_arguments = [ - "FP_PDN_RAIL_OFFSET", - "FP_PDN_RAIL_WIDTH", -]) +# +# VERILOG_FILES_BLACKBOX is a config.mk-local helper: only used via +# $(VERILOG_FILES_BLACKBOX) expansion inside VERILOG_FILES. +design( + config = "config.mk", + user_arguments = [ + "FP_PDN_RAIL_OFFSET", + "FP_PDN_RAIL_WIDTH", + ], + local_arguments = ["VERILOG_FILES_BLACKBOX"], +) diff --git a/flow/designs/sky130hd/microwatt/BUILD b/flow/designs/sky130hd/microwatt/BUILD index 527d6542e1..a375309357 100644 --- a/flow/designs/sky130hd/microwatt/BUILD +++ b/flow/designs/sky130hd/microwatt/BUILD @@ -1,3 +1,6 @@ load("//flow/designs:design.bzl", "design") -design(config = "config.mk") +# VERILOG_FILES_BLACKBOX is a config.mk-local helper: only used via +# $(VERILOG_FILES_BLACKBOX) expansion inside VERILOG_FILES. Not read by +# ORFS or by any user .tcl/.mk — drop it so it never reaches orfs_flow. +design(config = "config.mk", local_arguments = ["VERILOG_FILES_BLACKBOX"]) diff --git a/flow/scripts/variables.json b/flow/scripts/variables.json index 0ac1e23518..0c8e56ad77 100644 --- a/flow/scripts/variables.json +++ b/flow/scripts/variables.json @@ -1447,12 +1447,6 @@ "synth" ] }, - "VERILOG_FILES_BLACKBOX": { - "description": "Verilog files (typically `IPs/*.v`) that are appended to VERILOG_FILES in hierarchical designs and treated as blackbox modules by yosys. Only used by config.mk; ORFS doesn't read it as an env var.\n", - "stages": [ - "synth" - ] - }, "VERILOG_INCLUDE_DIRS": { "description": "Specifies the include directories for the Verilog input files.\n", "stages": [ diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 6c8d2300a6..c8cbfb7898 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -1585,11 +1585,3 @@ CDL_FILE: for generating Circuit Description Language output. stages: - final -VERILOG_FILES_BLACKBOX: - description: > - Verilog files (typically `IPs/*.v`) that are appended to - VERILOG_FILES in hierarchical designs and treated as blackbox - modules by yosys. Only used by config.mk; ORFS doesn't read it as - an env var. - stages: - - synth From e731422053d6e124c5972f38ac61522c927fc3b7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 11 May 2026 13:15:07 +0200 Subject: [PATCH 25/28] bazel: rename root BUILD to BUILD.bazel, drop empty WORKSPACE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Match the top-level package convention used by tools/OpenROAD/ (BUILD.bazel at the package root, plain BUILD in sub-packages). Adding bazel/BUILD in the previous commit turned bazel/ into a package, so the root BUILD's src reference "bazel/install.sh" became invalid; point it at the //bazel:install.sh label instead and export the file from bazel/BUILD. Drop the empty WORKSPACE — tools/OpenROAD/ already runs WORKSPACE-less and bazel 8 with no --enable_workspace runs bzlmod-only. Signed-off-by: Øyvind Harboe --- BUILD => BUILD.bazel | 2 +- WORKSPACE | 2 -- bazel/BUILD | 4 +++- 3 files changed, 4 insertions(+), 4 deletions(-) rename BUILD => BUILD.bazel (74%) delete mode 100644 WORKSPACE diff --git a/BUILD b/BUILD.bazel similarity index 74% rename from BUILD rename to BUILD.bazel index 21e694405f..a10ca06fab 100644 --- a/BUILD +++ b/BUILD.bazel @@ -2,5 +2,5 @@ load("@rules_shell//shell:sh_binary.bzl", "sh_binary") sh_binary( name = "install_for_bazel", - srcs = ["bazel/install.sh"], + srcs = ["//bazel:install.sh"], ) diff --git a/WORKSPACE b/WORKSPACE deleted file mode 100644 index 6ba4a02382..0000000000 --- a/WORKSPACE +++ /dev/null @@ -1,2 +0,0 @@ -# This file marks the root of the Bazel workspace. -# See MODULE.bazel for external dependencies setup. diff --git a/bazel/BUILD b/bazel/BUILD index d518110449..8544b0eb4e 100644 --- a/bazel/BUILD +++ b/bazel/BUILD @@ -1 +1,3 @@ -exports_files(glob(["*.patch"])) +exports_files( + glob(["*.patch"]) + ["install.sh"], +) From f2b03914c634ec3aa51fa5da4e3d7629c356838e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 11 May 2026 13:25:40 +0200 Subject: [PATCH 26/28] deps: bump bazel-orfs to PR #720 head, drop upstreamed patches MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit bazel-orfs PR https://github.com/The-OpenROAD-Project/bazel-orfs/pull/720 lands the two patches we were carrying as 0001/0002: - orfs_design() accepts config = "config.mk" explicitly and drops the blanket native.exports_files(native.glob(["*"])); - orfs_design() takes a local_arguments= list to drop config.mk helpers (e.g. VERILOG_FILES_BLACKBOX) before orfs_flow(). It also adds parser unit tests covering the VERILOG_FILES_BLACKBOX pattern that local_arguments= targets. Bump bazel-orfs to 717655415d (PR #720 head) and drop both patches. bazel/BUILD shrinks to a single exports_files(["install.sh"]) — the only remaining reason for the package is making //bazel:install.sh resolvable from //:install_for_bazel. Verified: bazelisk test //flow/designs/asap7/gcd/... passes; microwatt and chameleon (both consumers of local_arguments=) parse. Signed-off-by: Øyvind Harboe --- MODULE.bazel | 7 +- MODULE.bazel.lock | 2 +- ...pt-config-mk-explicitly-drop-exports.patch | 107 ------------------ ...-local_arguments-to-drop-helper-vars.patch | 42 ------- bazel/BUILD | 4 +- 5 files changed, 3 insertions(+), 159 deletions(-) delete mode 100644 bazel/0001-orfs_design-accept-config-mk-explicitly-drop-exports.patch delete mode 100644 bazel/0002-orfs_design-add-local_arguments-to-drop-helper-vars.patch diff --git a/MODULE.bazel b/MODULE.bazel index 33965e2714..1629312655 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -37,7 +37,7 @@ git_override( bazel_dep(name = "bazel-orfs", dev_dependency = True) bazel_dep(name = "bazel-orfs-verilog", dev_dependency = True) -BAZEL_ORFS_COMMIT = "b1ceeb28fc41b80b1fa85032e0770203847d4ba7" +BAZEL_ORFS_COMMIT = "717655415dd4446ca4e2fc09907465c75cb23912" BAZEL_ORFS_REMOTE = "https://github.com/The-OpenROAD-Project/bazel-orfs.git" @@ -45,11 +45,6 @@ BAZEL_ORFS_REMOTE = "https://github.com/The-OpenROAD-Project/bazel-orfs.git" git_override( module_name = "bazel-orfs", commit = BAZEL_ORFS_COMMIT, - patches = [ - "//bazel:0001-orfs_design-accept-config-mk-explicitly-drop-exports.patch", - "//bazel:0002-orfs_design-add-local_arguments-to-drop-helper-vars.patch", - ], - patch_strip = 1, remote = BAZEL_ORFS_REMOTE, ) diff --git a/MODULE.bazel.lock b/MODULE.bazel.lock index 7a654c8117..d6d739e628 100644 --- a/MODULE.bazel.lock +++ b/MODULE.bazel.lock @@ -752,7 +752,7 @@ }, "@@bazel-orfs+//:extension.bzl%orfs_repositories": { "general": { - "bzlTransitiveDigest": "n442YWYaiLaZmB140K7YjK80SbojjoPPnbiBKSmFuSk=", + "bzlTransitiveDigest": "C6+jSEpGuhiLoQhPNZaHk2lhRCKMAwa/llq72vzyygE=", "usagesDigest": "kN404VO76h9sN8hnC3NU50coiQwAhsXt84AqwipKiMg=", "recordedFileInputs": {}, "recordedDirentsInputs": {}, diff --git a/bazel/0001-orfs_design-accept-config-mk-explicitly-drop-exports.patch b/bazel/0001-orfs_design-accept-config-mk-explicitly-drop-exports.patch deleted file mode 100644 index d0d41d5dbb..0000000000 --- a/bazel/0001-orfs_design-accept-config-mk-explicitly-drop-exports.patch +++ /dev/null @@ -1,107 +0,0 @@ -diff --git a/private/designs.bzl b/private/designs.bzl -index e0bbc6c..9abde05 100644 ---- a/private/designs.bzl -+++ b/private/designs.bzl -@@ -146,8 +146,28 @@ def _orfs_designs_impl(repository_ctx): - "blocks": [], - } - -- # Generate designs.bzl -- bzl_content = "DESIGNS = %s\n" % repr(designs) -+ # Generate designs.bzl with both the raw DESIGNS dict (for backward -+ # compatibility) and an orfs_design() wrapper that bakes in DESIGNS -+ # so BUILD files can simply do: -+ # load("@orfs_designs//:designs.bzl", "orfs_design") -+ # orfs_design(config = "config.mk") -+ bzl_content = '''"""Auto-generated design configurations from config.mk files.""" -+ -+load("@bazel-orfs//private:orfs_design.bzl", _orfs_design = "orfs_design") -+ -+DESIGNS = %s -+ -+def orfs_design(config = "config.mk", **kwargs): -+ """Create orfs_flow() targets for this design. -+ -+ Args: -+ config: The config.mk file that drives this design. -+ Makes the BUILD file self-documenting. -+ **kwargs: Forwarded to the underlying orfs_design implementation -+ (platform, design, mock_openroad, mock_yosys, user_arguments). -+ """ -+ _orfs_design(config = config, designs = DESIGNS, **kwargs) -+''' % repr(designs) - repository_ctx.file("designs.bzl", bzl_content) - repository_ctx.file("BUILD.bazel", "") - -diff --git a/private/orfs_design.bzl b/private/orfs_design.bzl -index cb607fc..51e88f7 100644 ---- a/private/orfs_design.bzl -+++ b/private/orfs_design.bzl -@@ -1,7 +1,10 @@ - """Macro to create orfs_flow() targets from parsed config.mk data. - - Call orfs_design() from a design's BUILD.bazel to auto-generate --orfs_flow() targets based on the design's config.mk. -+orfs_flow() targets based on the design's config.mk: -+ -+ load("@orfs_designs//:designs.bzl", "orfs_design") -+ orfs_design(config = "config.mk") - - The orfs_designs repository rule (designs.bzl) must be instantiated - first to parse all config.mk files and generate the DESIGNS dict. -@@ -44,22 +47,26 @@ def _convert_sources(sources, pkg): - result[var] = converted - return result - --def orfs_design(name = None, platform = None, design = None, designs = None, mock_openroad = None, mock_yosys = None, user_arguments = []): # buildifier: disable=unused-variable -+def orfs_design(name = None, config = "config.mk", platform = None, design = None, designs = None, mock_openroad = None, mock_yosys = None, user_arguments = []): # buildifier: disable=unused-variable - """Create orfs_flow() targets for a design based on its parsed config.mk. - -- Call this from a design's BUILD.bazel: -- load("@bazel-orfs//:openroad.bzl", "orfs_design") -- load("@orfs_designs//:designs.bzl", "DESIGNS") -- orfs_design(designs = DESIGNS) -+ Usage: -+ -+ load("@orfs_designs//:designs.bzl", "orfs_design") -+ orfs_design(config = "config.mk") - - The platform and design are auto-detected from the package path - (flow/designs///). - - Args: - name: Unused, required by Bazel macro convention. -+ config: The config.mk file that drives this design. Makes the -+ BUILD file self-documenting about what configures the build. - platform: Override platform (default: from package path). - design: Override design nickname (default: from package path). - designs: The DESIGNS dict from the orfs_designs repository rule. -+ Supplied automatically by the generated wrapper in -+ @orfs_designs//:designs.bzl. - mock_openroad: Label for mock-openroad binary. When set, generates - lint flow targets (variant="lint") alongside real flow targets. - Example: "//mock/openroad/src/bin:openroad". -@@ -74,16 +81,17 @@ def orfs_design(name = None, platform = None, design = None, designs = None, moc - ORFS arguments. - """ - if designs == None: -- fail("orfs_design() requires designs argument: pass DESIGNS from @orfs_designs//:designs.bzl") -+ fail("orfs_design() requires designs: load orfs_design from @orfs_designs//:designs.bzl") - -- native.exports_files( -- native.glob(["*"]), -- visibility = ["//visibility:public"], -- ) -+ # Validate that the config file exists in this package -+ if not native.glob([config], allow_empty = True): -+ fail("orfs_design(): config file %s not found in %s" % (config, native.package_name())) - -- # Create filegroups for wildcard source patterns (e.g. ADDITIONAL_LEFS) -+ # Create filegroups for design files so they are accessible to -+ # orfs_flow() rules without using exports_files(). - existing_rules = native.existing_rules() - for fg_name, fg_glob in [ -+ ("design_config", ["*.mk", "*.sdc", "*.json", "*.cfg", "*.tcl", "*.def"]), - ("lef", ["*.lef"]), - ("lib", ["*.lib"]), - ("gds", ["*.gds.gz"]), diff --git a/bazel/0002-orfs_design-add-local_arguments-to-drop-helper-vars.patch b/bazel/0002-orfs_design-add-local_arguments-to-drop-helper-vars.patch deleted file mode 100644 index 83811d1c3c..0000000000 --- a/bazel/0002-orfs_design-add-local_arguments-to-drop-helper-vars.patch +++ /dev/null @@ -1,42 +0,0 @@ -diff --git a/private/orfs_design.bzl b/private/orfs_design.bzl ---- a/private/orfs_design.bzl -+++ b/private/orfs_design.bzl -@@ -47,7 +47,7 @@ - result[var] = converted - return result - --def orfs_design(name = None, config = "config.mk", platform = None, design = None, designs = None, mock_openroad = None, mock_yosys = None, user_arguments = []): # buildifier: disable=unused-variable -+def orfs_design(name = None, config = "config.mk", platform = None, design = None, designs = None, mock_openroad = None, mock_yosys = None, user_arguments = [], local_arguments = []): # buildifier: disable=unused-variable - """Create orfs_flow() targets for a design based on its parsed config.mk. - - Usage: -@@ -79,6 +79,12 @@ - Routed through orfs_flow(user_arguments=...) to bypass the - variables.yaml validator instead of being checked as known - ORFS arguments. -+ local_arguments: List of variable names that are only used for -+ $(VAR) expansion within the same config.mk and are not read -+ by ORFS or by any user .tcl/.mk (e.g. VERILOG_FILES_BLACKBOX, -+ which appears verbatim inside VERILOG_FILES). These are -+ dropped entirely before orfs_flow() is invoked — neither -+ validated against variables.yaml nor exposed as env vars. - """ - if designs == None: - fail("orfs_design() requires designs: load orfs_design from @orfs_designs//:designs.bzl") -@@ -172,6 +178,16 @@ - # Real flow — uses Docker image with real OpenROAD/Yosys - arguments = dict(config["arguments"]) - -+ # Drop caller-flagged local helper vars used only via $(VAR) -+ # expansion within the same config.mk (e.g. VERILOG_FILES_BLACKBOX). -+ # They must not reach orfs_flow — they would either fail validation -+ # or be exposed as noise env vars. The config.mk parser may classify -+ # such helpers as either arguments or sources (e.g. when they expand -+ # to file globs), so drop from both. -+ for var in local_arguments: -+ arguments.pop(var, None) -+ sources.pop(var, None) -+ - # Move caller-flagged design-specific knobs out of arguments and into - # user_arguments so they bypass the variables.yaml validator. - user_args = {} diff --git a/bazel/BUILD b/bazel/BUILD index 8544b0eb4e..3a4d272969 100644 --- a/bazel/BUILD +++ b/bazel/BUILD @@ -1,3 +1 @@ -exports_files( - glob(["*.patch"]) + ["install.sh"], -) +exports_files(["install.sh"]) From b4ab3c574dfb5ac0f488d88f6d7bbd82c1349b63 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 11 May 2026 13:28:28 +0200 Subject: [PATCH 27/28] bazel: revert install_for_bazel drive-by changes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit bazel/BUILD only existed to export the bazel-orfs patches I had introduced. Since those patches landed upstream (bazel-orfs PR #720) and were removed in the previous commit, the package is no longer needed. Dropping it lets //:install_for_bazel reference bazel/install.sh as a same-package file again, the way it has been on master since PR #4003 — so this PR no longer touches that rule. Signed-off-by: Øyvind Harboe --- BUILD.bazel | 2 +- bazel/BUILD | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) delete mode 100644 bazel/BUILD diff --git a/BUILD.bazel b/BUILD.bazel index a10ca06fab..21e694405f 100644 --- a/BUILD.bazel +++ b/BUILD.bazel @@ -2,5 +2,5 @@ load("@rules_shell//shell:sh_binary.bzl", "sh_binary") sh_binary( name = "install_for_bazel", - srcs = ["//bazel:install.sh"], + srcs = ["bazel/install.sh"], ) diff --git a/bazel/BUILD b/bazel/BUILD deleted file mode 100644 index 3a4d272969..0000000000 --- a/bazel/BUILD +++ /dev/null @@ -1 +0,0 @@ -exports_files(["install.sh"]) From 67fad13b7f1d060ee0950331387a004a5dc68df7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 11 May 2026 16:19:46 +0200 Subject: [PATCH 28/28] bazel: rename flow/bazel-orfs.md to flow/README.md MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The security scan blocks `flow/bazel-orfs.md` by filename. Move the content to `flow/README.md` and update the MODULE.bazel reference. Co-Authored-By: Claude Opus 4.7 (1M context) Signed-off-by: Øyvind Harboe --- MODULE.bazel | 2 +- flow/{bazel-orfs.md => README.md} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename flow/{bazel-orfs.md => README.md} (100%) diff --git a/MODULE.bazel b/MODULE.bazel index 1629312655..46f6288ab8 100644 --- a/MODULE.bazel +++ b/MODULE.bazel @@ -110,7 +110,7 @@ use_repo(orfs, "gnumake") use_repo(orfs, "orfs_variable_metadata") # Auto-generate orfs_flow() targets from config.mk files. -# See flow/bazel-orfs.md for usage. +# See flow/README.md for usage. orfs_designs = use_repo_rule("@bazel-orfs//private:designs.bzl", "orfs_designs") orfs_designs( diff --git a/flow/bazel-orfs.md b/flow/README.md similarity index 100% rename from flow/bazel-orfs.md rename to flow/README.md