Upstream update available: designs/src/bp_processor/dev/repo

[claude]

Upstream update available: designs/src/bp_processor/dev/repo

Field	Value
Pinned	f6619cb (2026-02-09)
Upstream	05ef10d (2026-04-24)
Commits behind	28
Days stale	74

Severity: MODERATE

The diff is a mix of RTL bug fixes and non-RTL improvements. Several RTL-level bugs were fixed (interrupt priority ordering, CSR fault PC write, CCE decode/pending-bits issues) that could affect simulation correctness and synthesis output. The rest is docs, CI, and tooling.

What changed

• RTL bug fixes:
  • bp_be_csr: fix instret_en to use is_s_mode instead of is_m_mode (#1262)
  • bp_be_csr: write faulting PC to mtval/stval on instruction access fault (fixes #1018) (#1270)
  • bp_be: fix interrupt priority ordering (fixes #1287) (#1288)
  • Fix CCE decode-dir case bug (#1289)
  • Fix CCE pending bits saturation (#1292)
  • TB: Fix associative array nonblocking assignment for Verilator 5.045 (#1290)
• Non-synthesizable / TB fixes:
  • Fix DRAM assertion (#1246); TB safety check for mem NOC CID aliasing (#1245)
  • CCE tracer: fix inconsistent signal usage (#1274)
  • DPI-C init: use plusargs for program name (#1277)
  • ICache tracer converted to plusargs (#1257)
• CI additions: xcelium support (#1304), coverage for VCS and Verilator (#1305), CI script update to v1p1
• Docs: inline docs for bp_be_commit_pkt_s fields, README improvements, Docker setup guide for macOS
• Tools: add root .editorconfig, make: export BP_DIR from Makefile.env

Recommendation

Update when convenient. The RTL bug fixes (interrupt priority, CSR behaviour) are correctness improvements that should be incorporated. None appear likely to break the HighTide synthesis flow, but the interrupt-priority fix in particular may shift timing-critical paths. Re-run affected bp_uno and bp_quad designs after updating.

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Last refreshed: 2026-05-04T09:41:35Z