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Copy pathfeature.c
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319 lines (311 loc) · 9.08 KB
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#include "riscv_asm.h"
#include "riscv_encoding.h"
#define FLAG_RV64XT32 0x1
#define FLAG_COPINSTEE 0x2
#define FLAG_XTINSTEE 0x4
extern unsigned long _load_start;
static inline void setup_boot_flag(void)
{
#if __riscv_xlen == 64
unsigned int boot_flag;
boot_flag = *(unsigned int *)(_load_start + 0x00008000 - 0x100);
if (boot_flag & FLAG_RV64XT32)
csr_write(CSR_MXSTATUS, csr_read(CSR_MXSTATUS) | (1ULL << 63));
if (boot_flag & FLAG_COPINSTEE) {
csr_set(CSR_MXSTATUS, 1ULL << 24);
csr_clear(CSR_MXSTATUS, 1ULL << 22);
}
if (boot_flag & FLAG_XTINSTEE)
csr_set(CSR_MXSTATUS, 1ULL << 22);
#endif
}
void setup_features(void)
{
unsigned int i, idx, cpu_type = 0, cpu_ver = 0xFFFF, cpu_tnmodel = 0xFFFF;
volatile unsigned long version = 0;
for (i = 7; i != 0; i--) {
version = csr_read(CSR_MCPUID);
idx = (version >> 28) & 0xf;
if (idx == 0) {
cpu_type = (version >> 18) & 0xf;
cpu_tnmodel = (version >> 14) & 0x1;
} else if (idx == 1) {
cpu_ver = (version >> 12) & 0xffff;
}
if (cpu_ver != 0xFFFF && cpu_tnmodel != 0xFFFF) {
break;
}
}
/*
* Warning: CSR_MCCR2 contains an L2 cache latency setting,
* you need to confirm it by your own soc design.
*/
switch (cpu_type) {
case 0x1:
if (cpu_ver >= 0x0) {
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x1ee30c);
csr_write(CSR_MHCR, 0x11ff);
csr_write(CSR_MHINT2,0x180);
} else {
while(1);
}
break;
case 0x2:
if (cpu_ver >= 0x0) {
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xa042000a);
csr_write(CSR_MXSTATUS, 0x438100);
csr_write(CSR_MHINT, 0x21aa10c);
csr_write(CSR_MHCR, 0x10011ff);
csr_write(CSR_MHINT4, 0x10000080);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else {
while(1);
}
break;
case 0x3:
if (cpu_ver >= 0x1080 && cpu_ver <= 0x10bf) { //1.2.0~1.2.x
csr_write(CSR_MCCR2, 0xe0010009);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x6e30c);
csr_write(CSR_MHCR, 0x1ff);
} else if (cpu_ver == 0x10ca) { //1.3.10
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe2490009);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x66e30c);
csr_write(CSR_MHCR, 0x17f);
csr_write(CSR_MHINT2, 0x420000);
csr_write(CSR_MHINT4, 0x410);
} else if (cpu_ver >= 0x1100 && cpu_ver <= 0x113f) { //1.4.0~1.4.x
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe2490009);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x16e30c);
csr_write(CSR_MHCR, 0x1ff);
} else if (cpu_ver >= 0x1140 && cpu_ver <= 0x117f) { //1.5.0~1.5.x
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe2490009);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0xe6e30c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x1ff);
} else if (cpu_ver >= 0x1180 && cpu_ver <= 0x1183) { //1.6.0~1.6.3
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x1ee30c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x1ff);
} else if (cpu_ver >= 0x1184 && cpu_ver <= 0x123f) { //1.6.4~1.8.x
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x1ee30c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x11ff);
} else if (cpu_ver >= 0x2000 && cpu_ver <= 0x200e) { //2.0.0~2.0.14
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x438000);
csr_write(CSR_MHINT, 0x31ea32c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x11ff);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x200f && cpu_ver <= 0x2045) { //2.0.15~2.1.5
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x438000);
csr_write(CSR_MHINT, 0x11ea32c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x11ff);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x2046 && cpu_ver <= 0x20c3) { //2.1.6~2.3.3
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x438000);
csr_write(CSR_MHINT, 0x31ea32c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x11ff);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x20c4 && cpu_ver <= 0x2fff) { //2.3.4~2.x.x
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x438100);
csr_write(CSR_MHINT, 0x31ea32c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x11ff);
csr_write(CSR_MHINT4, 0x2080);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x3000 && cpu_ver <= 0x3fff) { //3.0.0~3.x.x
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe249000b);
csr_write(CSR_MXSTATUS, 0x438100);
csr_write(CSR_MHINT, 0x31ea32c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x11ff);
csr_write(CSR_MHINT4, 0x2080);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x4000 && cpu_ver <= 0x4fff) { //4.0.0~4.x.x
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe24a000a);
csr_write(CSR_MXSTATUS, 0xc0c38000);
csr_write(CSR_MHINT, 0x31ea32c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x11ff);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x5000 && cpu_ver <= 0x5fff) { //5.0.0~5.x.x
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe24a000a);
csr_write(CSR_MXSTATUS, 0xc0c38000);
csr_write(CSR_MHINT, 0x31ea12c);
csr_write(CSR_MHINT2, 0x180);
csr_write(CSR_MHCR, 0x11ff);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else {
while(1);
}
break;
case 0x4:
if (cpu_ver >= 0x1002 && cpu_ver <= 0xffff) {
csr_write(CSR_MHCR, 0x17f);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x650c);
} else {
while(1);
}
break;
case 0x5:
if(cpu_tnmodel == 0) { //c908
if (cpu_ver >= 0x0000 && cpu_ver <= 0x0007) { //0.0.0~0.0.7
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xe0420008);
csr_write(CSR_MXSTATUS, 0x638000);
csr_write(CSR_MHINT, 0x2c50c);
csr_write(CSR_MHCR, 0x11ff);
} else if (cpu_ver >= 0x0040 && cpu_ver <= 0x1002) { //0.1.0~1.0.2
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xa042000a);
csr_write(CSR_MXSTATUS, 0x438000);
csr_write(CSR_MHINT, 0x21aa10c);
csr_write(CSR_MHCR, 0x10011ff);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x1003 && cpu_ver <= 0x100b) { //1.0.3~1.0.11
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xa042000a);
csr_write(CSR_MXSTATUS, 0x438000);
csr_write(CSR_MHINT, 0x1aa10c);
csr_write(CSR_MHCR, 0x10011ff);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x100c && cpu_ver <= 0x1fff) { //1.0.12~
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xa042000a);
csr_write(CSR_MXSTATUS, 0x438100);
csr_write(CSR_MHINT, 0x21aa10c);
csr_write(CSR_MHCR, 0x10011ff);
csr_write(CSR_MHINT4, 0x10000080);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x2000 && cpu_ver <= 0xffff) { //2.0.0~
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xa042000a);
csr_write(CSR_MXSTATUS, 0x438100);
csr_write(CSR_MHINT, 0x21aa10c);
csr_write(CSR_MHCR, 0x10011ff);
csr_write(CSR_MHINT4, 0x10000080);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else {
while(1);
}
} else if (cpu_tnmodel == 1) {
if (cpu_ver >= 0x0) {
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xA0420002);
csr_write(CSR_MXSTATUS, 0x438100);
csr_write(CSR_MHINT, 0x21AA10C);
csr_write(CSR_MHCR, 0x10011FF);
csr_write(CSR_MHINT4, 0x10000080);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else {
while(1);
}
} else {
while(1);
}
break;
case 0x6:
if (cpu_ver >= 0x0) {
csr_write(CSR_MSMPR, 0x1);
csr_write(CSR_MCCR2, 0xA0420002);
csr_write(CSR_MXSTATUS, 0x438000);
csr_write(CSR_MHINT, 0x3A1AA10C);
csr_write(CSR_MHCR, 0x10011BF);
#if __riscv_xlen == 64
csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else {
while(1);
}
break;
case 0x7:
if (cpu_ver >= 0x0) {
csr_clear(CSR_MXSTATUS, 0x1);
csr_write(CSR_MISELECT,CSR_MNASTATUS);
csr_write(CSR_MIREG,0x1e);
} else {
while(1);
}
break;
case 0x8:
if (cpu_ver >= 0x0) {
csr_clear(CSR_MXSTATUS, 0x1);
csr_write(CSR_MISELECT,CSR_MNASTATUS);
csr_write(CSR_MIREG,0x1e);
} else {
while(1);
}
break;
case 0x9:
if(cpu_ver >= 0x0) {
csr_clear(CSR_MXSTATUS, 0x1);
csr_write(CSR_MISELECT,CSR_MNASTATUS);
csr_write(CSR_MIREG,0x1e);
csr_write(CSR_MISELECT, CSR_L2_TRA_CTRL);
csr_set(CSR_MIREG2, 0x1600);
} else {
while(1);
}
break;
default:
while(1);
}
setup_boot_flag();
}