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* From Venice SBRMI device ID is 1, instead of checking each device PID, we should check for the Instance ID. Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com>
* From Venice SBTSI device ID is 0, instead of checking each device PID, we should check for the Instance ID. Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com>
…A, Fam:0x50
- SBRMI/TSI devices for new APML has PID as per below description.
[11:0] Additional ID: 0x118
[15:12] SB-TSI(0x0)
[31:16] [16]: DIE_ID, [25:24]: SOCKET ID
sock 0 die 0: 0x0
sock 0 die 1: 0x1
sock 1 die 0: 0x100
sock 1 die 1: 0x101
[32]: PID type select, it is 0 now to select fixed vendor value;
[47:33]: Manufacture ID, MIPI alliance has allocated the value for each company, AMD should be 0x0112
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
Signed-off-by: Akshay Gupta <akshay.gupta@amd.com>
…A, Fam:0x50 - PID for SBRMI devices in Fam:0x1A, Fam:0x50 is defines as: [11:0] Additional ID: 0x118 [15:12] SB-TSI(0x0)/SB-RMI(0x1) [31:16] [16]: DIE_ID, [25:24]: SOCKET ID sock 0 die 0: 0x0 sock 0 die 1: 0x1 sock 1 die 0: 0x100 sock 1 die 1: 0x101 [32]: PID type select, it is 0 now to select fixed vendor value; [47:33]: Manufacture ID, MIPI alliance has allocated the value for each company, AMD should be 0x0112 Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com>
- Extra info, part of PID is standard and should not be change. This device id will be used by other drivers, which can break. Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com>
…umber Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com>
…id number Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com>
Processors from AMD provide APML ALERT_L for BMC users to monitor events. APML Alert_L is asserted in multiple events, - Machine Check Exception occurs within the system - The processor alerts the SBI on system fatal error event - Set by hardware as a result of a 0x71/0x72/0x73 command completion - Set by firmware to indicate the completion of a mailbox operation - High/Low Temperature Alert APML Alert_L module define uevents to notify registered userspace processes of the alert event. Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Signed-off-by: sathya priya kumar <SathyaPriya.K@amd.com>
-Add alertl node for morocco and congo platforms Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Signed-off-by: Sathya Priya Kumar <SathyaPriya.K@amd.com>
Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Signed-off-by: sathya priya kumar <SathyaPriya.K@amd.com>
| static const struct i3c_device_id sbrmi_i3c_id[] = { | ||
| I3C_DEVICE_EXTRA_INFO(0, 0x000, 0x1118, NULL), /* P0 - IOD0 - SBRMI */ | ||
| I3C_DEVICE_EXTRA_INFO(0, 0x100, 0x1118, NULL), /* P1 - IOD0 - SBRMI */ | ||
| I3C_DEVICE_EXTRA_INFO(0, 0x000, 0x118, NULL), /* P0 - IOD0 - SBRMI */ |
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sbrmi ID is 0x1118 for Venice. pls check
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i3c_device_match_id function is defined in file drivers/i3c/device.c where the manu_id, partid, ext_info are extracted and matched.
ext_info is assigned in file, drivers/i3c/device.c as
ext_info = I3C_PID_EXTRA_INFO(devinfo.pid);
where I3C_PID_EXTRA_INFO is defined in file "include/linux/i3c/device.h" as
#define I3C_PID_EXTRA_INFO(pid) ((pid) & GENMASK_ULL(11, 0))
ext_info is 12 bit value, the bits [15:12] are the instance ID, which is not part of ext_info
| I3C_DEVICE_EXTRA_INFO(0, 0x000, 0x1118, NULL), /* P0 - IOD0 - SBRMI */ | ||
| I3C_DEVICE_EXTRA_INFO(0, 0x100, 0x1118, NULL), /* P1 - IOD0 - SBRMI */ | ||
| I3C_DEVICE_EXTRA_INFO(0x112, 0x0, 0x2, NULL), | ||
| I3C_DEVICE_EXTRA_INFO(0x112, 0x0, 0x118, NULL), /* Socket:0, IOD:0 */ |
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sbrmi additional id is 0x1118 not 0x118.
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This change works on top of the DMA patches where the OR instance ID is removed.
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i3c_device_match_id function is defined in file drivers/i3c/device.c where the manu_id, partid, ext_info are extracted and matched.
ext_info is assigned in file, drivers/i3c/device.c as
ext_info = I3C_PID_EXTRA_INFO(devinfo.pid);
where I3C_PID_EXTRA_INFO is defined in file "include/linux/i3c/device.h" as
#define I3C_PID_EXTRA_INFO(pid) ((pid) & GENMASK_ULL(11, 0))
ext_info is 12 bit value, the bits [15:12] are the instance ID, which is not part of ext_info
| sbtsi = <&sbtsi_p0_iod0>; | ||
| }; | ||
| }; | ||
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Please add Alert_L node for socket 1.
You can get the LTPI GPIO number from the PR #139
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Akshay, Can you please seperate this PR into multiple PRs
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Hi @srgovard This PR and the DMA patch from https://ontrack-internal.amd.com/browse/FWDEV-126844 into the linux-aspeed are modifying the same files. please sequence them appropriately. |
6 participants
APML modules patches to support Venice.
APML Alert_L module support for Venice.