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Use FMOV instead of INS. #445

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5e1a255
Use FMOV instead of INS.
MartinWehking Jul 17, 2026
19ab527
Remove extra '/'
MartinWehking Jul 20, 2026
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14 changes: 5 additions & 9 deletions neon_intrinsics/advsimd.md
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Expand Up @@ -2620,10 +2620,6 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
| <code>int64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128" target="_blank">vreinterpretq_s64_p128</a>(poly128_t a)</code> | `a -> Vd.1Q` | `NOP` | `Vd.2D -> result` | `A32/A64` |
| <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128" target="_blank">vreinterpretq_f64_p128</a>(poly128_t a)</code> | `a -> Vd.1Q` | `NOP` | `Vd.2D -> result` | `A64` |
| <code>float16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128" target="_blank">vreinterpretq_f16_p128</a>(poly128_t a)</code> | `a -> Vd.1Q` | `NOP` | `Vd.8H -> result` | `A32/A64` |
| <code>mfloat8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_mf8_u8" target="_blank">vreinterpret_mf8_u8</a>(uint8x8_t a)</code> | `a -> Vd.8B` | `NOP` | `Vd.8B -> result` | `A64` |
| <code>mfloat8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_mf8_u8" target="_blank">vreinterpretq_mf8_u8</a>(uint8x16_t a)</code> | `a -> Vd.16B` | `NOP` | `Vd.16B -> result` | `A64` |
| <code>uint8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_mf8" target="_blank">vreinterpret_u8_mf8</a>(mfloat8x8_t a)</code> | `a -> Vd.8B` | `NOP` | `Vd.8B -> result` | `A64` |
| <code>uint8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_mf8" target="_blank">vreinterpretq_u8_mf8</a>(mfloat8x16_t a)</code> | `a -> Vd.16B` | `NOP` | `Vd.16B -> result` | `A64` |

### Move

Expand Down Expand Up @@ -3250,25 +3246,25 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
| <code>int16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16" target="_blank">vdupq_n_s16</a>(int16_t value)</code> | `value -> rn` | `DUP Vd.8H,rn` | `Vd.8H -> result` | `v7/A32/A64` |
| <code>int32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32" target="_blank">vdup_n_s32</a>(int32_t value)</code> | `value -> rn` | `DUP Vd.2S,rn` | `Vd.2S -> result` | `v7/A32/A64` |
| <code>int32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32" target="_blank">vdupq_n_s32</a>(int32_t value)</code> | `value -> rn` | `DUP Vd.4S,rn` | `Vd.4S -> result` | `v7/A32/A64` |
| <code>int64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64" target="_blank">vdup_n_s64</a>(int64_t value)</code> | `value -> rn` | `INS Dd.D[0],xn` | `Vd.1D -> result` | `v7/A32/A64` |
| <code>int64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64" target="_blank">vdup_n_s64</a>(int64_t value)</code> | `value -> Xn` | `FMOV Dd,Xn` | `Vd.1D -> result` | `v7/A32/A64` |
| <code>int64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64" target="_blank">vdupq_n_s64</a>(int64_t value)</code> | `value -> rn` | `DUP Vd.2D,rn` | `Vd.2D -> result` | `v7/A32/A64` |
| <code>uint8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8" target="_blank">vdup_n_u8</a>(uint8_t value)</code> | `value -> rn` | `DUP Vd.8B,rn` | `Vd.8B -> result` | `v7/A32/A64` |
| <code>uint8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8" target="_blank">vdupq_n_u8</a>(uint8_t value)</code> | `value -> rn` | `DUP Vd.16B,rn` | `Vd.16B -> result` | `v7/A32/A64` |
| <code>uint16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u16" target="_blank">vdup_n_u16</a>(uint16_t value)</code> | `value -> rn` | `DUP Vd.4H,rn` | `Vd.4H -> result` | `v7/A32/A64` |
| <code>uint16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16" target="_blank">vdupq_n_u16</a>(uint16_t value)</code> | `value -> rn` | `DUP Vd.8H,rn` | `Vd.8H -> result` | `v7/A32/A64` |
| <code>uint32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32" target="_blank">vdup_n_u32</a>(uint32_t value)</code> | `value -> rn` | `DUP Vd.2S,rn` | `Vd.2S -> result` | `v7/A32/A64` |
| <code>uint32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32" target="_blank">vdupq_n_u32</a>(uint32_t value)</code> | `value -> rn` | `DUP Vd.4S,rn` | `Vd.4S -> result` | `v7/A32/A64` |
| <code>uint64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64" target="_blank">vdup_n_u64</a>(uint64_t value)</code> | `value -> rn` | `INS Dd.D[0],xn` | `Vd.1D -> result` | `v7/A32/A64` |
| <code>uint64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64" target="_blank">vdup_n_u64</a>(uint64_t value)</code> | `value -> Xn` | `FMOV Dd,Xn` | `Vd.1D -> result` | `v7/A32/A64` |
| <code>uint64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u64" target="_blank">vdupq_n_u64</a>(uint64_t value)</code> | `value -> rn` | `DUP Vd.2D,rn` | `Vd.2D -> result` | `v7/A32/A64` |
| <code>poly64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p64" target="_blank">vdup_n_p64</a>(poly64_t value)</code> | `value -> rn` | `INS Dd.D[0],xn` | `Vd.1D -> result` | `A32/A64` |
| <code>poly64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p64" target="_blank">vdup_n_p64</a>(poly64_t value)</code> | `value -> Xn` | `FMOV Dd,Xn` | `Vd.1D -> result` | `A32/A64` |
| <code>poly64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p64" target="_blank">vdupq_n_p64</a>(poly64_t value)</code> | `value -> rn` | `DUP Vd.2D,rn` | `Vd.2D -> result` | `A32/A64` |
| <code>float32x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32" target="_blank">vdup_n_f32</a>(float32_t value)</code> | `value -> rn` | `DUP Vd.2S,rn` | `Vd.2S -> result` | `v7/A32/A64` |
| <code>float32x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32" target="_blank">vdupq_n_f32</a>(float32_t value)</code> | `value -> rn` | `DUP Vd.4S,rn` | `Vd.4S -> result` | `v7/A32/A64` |
| <code>poly8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p8" target="_blank">vdup_n_p8</a>(poly8_t value)</code> | `value -> rn` | `DUP Vd.8B,rn` | `Vd.8B -> result` | `v7/A32/A64` |
| <code>poly8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p8" target="_blank">vdupq_n_p8</a>(poly8_t value)</code> | `value -> rn` | `DUP Vd.16B,rn` | `Vd.16B -> result` | `v7/A32/A64` |
| <code>poly16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p16" target="_blank">vdup_n_p16</a>(poly16_t value)</code> | `value -> rn` | `DUP Vd.4H,rn` | `Vd.4H -> result` | `v7/A32/A64` |
| <code>poly16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p16" target="_blank">vdupq_n_p16</a>(poly16_t value)</code> | `value -> rn` | `DUP Vd.8H,rn` | `Vd.8H -> result` | `v7/A32/A64` |
| <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f64" target="_blank">vdup_n_f64</a>(float64_t value)</code> | `value -> rn` | `INS Dd.D[0],xn` | `Vd.1D -> result` | `A64` |
| <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f64" target="_blank">vdup_n_f64</a>(float64_t value)</code> | `value -> Xn` | `FMOV Dd,Xn` | `Vd.1D -> result` | `A64` |
| <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f64" target="_blank">vdupq_n_f64</a>(float64_t value)</code> | `value -> rn` | `DUP Vd.2D,rn` | `Vd.2D -> result` | `A64` |
| <code>mfloat8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_mf8" target="_blank">vdup_n_mf8</a>(mfloat8_t value)</code> | `value -> rn` | `DUP Vd.8B,rn` | `Vd.8B -> result` | `A64` |
| <code>mfloat8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_mf8" target="_blank">vdupq_n_mf8</a>(mfloat8_t value)</code> | `value -> rn` | `DUP Vd.16B,rn` | `Vd.16B -> result` | `A64` |
Expand Down Expand Up @@ -3324,7 +3320,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``.
| <code>poly16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16" target="_blank">vdupq_lane_p16</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; poly16x4_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `vec -> Vn.4H`<br>`0 <= lane <= 3` | `DUP Vd.8H,Vn.H[lane]` | `Vd.8H -> result` | `v7/A32/A64` |
| <code>float64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64" target="_blank">vdup_lane_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `vec -> Vn.1D`<br>`0 <= lane <= 0` | `DUP Dd,Vn.D[lane]` | `Dd -> result` | `A64` |
| <code>float64x2_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64" target="_blank">vdupq_lane_f64</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; float64x1_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `vec -> Vn.1D`<br>`0 <= lane <= 0` | `DUP Vd.2D,Vn.D[lane]` | `Vd.2D -> result` | `A64` |
| <code>mfloat8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_mf8" target="_blank">vdup_lane_mf8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; mfloat8x8_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `vec -> Vn.8B`<br>`0 <= lane <= 7` | `DUP Vd.8B,Vn.B[lane]` | `Vd.8B -> result` | `/A64` |
| <code>mfloat8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_mf8" target="_blank">vdup_lane_mf8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; mfloat8x8_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `vec -> Vn.8B`<br>`0 <= lane <= 7` | `DUP Vd.8B,Vn.B[lane]` | `Vd.8B -> result` | `A64` |
| <code>mfloat8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_mf8" target="_blank">vdupq_lane_mf8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; mfloat8x8_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `vec -> Vn.8B`<br>`0 <= lane <= 7` | `DUP Vd.16B,Vn.B[lane]` | `Vd.16B -> result` | `A64` |
| <code>int8x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8" target="_blank">vdup_laneq_s8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int8x16_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `vec -> Vn.16B`<br>`0 <= lane <= 15` | `DUP Vd.8B,Vn.B[lane]` | `Vd.8B -> result` | `A64` |
| <code>int8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8" target="_blank">vdupq_laneq_s8</a>(<br>&nbsp;&nbsp;&nbsp;&nbsp; int8x16_t vec,<br>&nbsp;&nbsp;&nbsp;&nbsp; const int lane)</code> | `vec -> Vn.16B`<br>`0 <= lane <= 15` | `DUP Vd.16B,Vn.B[lane]` | `Vd.16B -> result` | `A64` |
Expand Down
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