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VLSI_RTLs
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51 Commits
51 Commits
4 bit Adder cum Subtractor
4 bit Adder cum Subtractor
4 bit Divider
4 bit Divider
4 bit Multiplier
4 bit Multiplier
4 bit Parallel Adder
4 bit Parallel Adder
Asynchronous and Synchronous Reset
Asynchronous and Synchronous Reset
BCD to 7-Segment Converter
BCD to 7-Segment Converter
BCD to Excess-3 code Converter
BCD to Excess-3 code Converter
Basic Logic Gates using Decoder
Basic Logic Gates using Decoder
Basic Logic Gates using Dmux
Basic Logic Gates using Dmux
Basic Logic Gates using Mux
Basic Logic Gates using Mux
Behavioural Modeling
Behavioural Modeling
Binary to 2's Complement Converter
Binary to 2's Complement Converter
Binary to BCD Converter
Binary to BCD Converter
Binary to Gray code Converter
Binary to Gray code Converter
Booth's Multiplication Algorithm
Booth's Multiplication Algorithm
Carry LookAhead Generator
Carry LookAhead Generator
Carry Select Adder
Carry Select Adder
Carry Skip Adder
Carry Skip Adder
D Flip Flop
D Flip Flop
DeMultiplexer [1x2]
DeMultiplexer [1x2]
DeMultiplexer [1x8] using [1x2]
DeMultiplexer [1x8] using [1x2]
Decoder [3x8]
Decoder [3x8]
Encoder [8x3]
Encoder [8x3]
Even Parity Generator and Checker
Even Parity Generator and Checker
Full Adder using Mux
Full Adder using Mux
Gate Modeling
Gate Modeling
Gray code to Binary Converter
Gray code to Binary Converter
Half Adder & Full Adder
Half Adder & Full Adder
Half Adder, Full Adder, Half Subtractor, Full Subtractor using Nand Gate
Half Adder, Full Adder, Half Subtractor, Full Subtractor using Nand Gate
Half Subtractor & Full Subtractor
Half Subtractor & Full Subtractor
Input Majority Circuit [7 input]
Input Majority Circuit [7 input]
JK Flip Flop
JK Flip Flop
Multiplexer [2x1]
Multiplexer [2x1]
Multiplexer [4x1] using [2x1]
Multiplexer [4x1] using [2x1]
N bit Comparator
N bit Comparator
N bit number Square [N -- N^2]
N bit number Square [N -- N^2]
Priority Encoder
Priority Encoder
SR Latch
SR Latch
Special Logic Gates using Dmux
Special Logic Gates using Dmux
Special Logic Gates using Mux
Special Logic Gates using Mux
Structral Modeling
Structral Modeling
Switch Level Modeling
Switch Level Modeling
T Flip Flop
T Flip Flop
Universal Logic Gate using Switch Level Modeling
Universal Logic Gate using Switch Level Modeling
Universal Logic Gates using Decoder
Universal Logic Gates using Decoder
Universal Logic Gates using Dmux
Universal Logic Gates using Dmux
Universal Logic Gates using Mux
Universal Logic Gates using Mux
Vedic Multiplier [2×2]
Vedic Multiplier [2×2]
Vedic Multiplier [4×4] using [2×2]
Vedic Multiplier [4×4] using [2×2]
README.md
README.md
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VLSI_RTLs
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