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asap7/coralnpu: fix detailed routing DRC violations at lower utilization - #4666
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When CORE_UTILIZATION is set to 55 or lower, the platform placement density was unconstrained and defaulted to 0.60, causing local cell congestion adjacent to fakeram macros and leading to unresolvable M2 shorts and M3 metal spacing violations in detailed routing. Add PLACE_DENSITY_LB_ADDON = 0.20 and horizontal cell padding (CELL_PAD_IN_SITES_GLOBAL_PLACEMENT = 1, CELL_PAD_IN_SITES_DETAIL_PLACEMENT = 1) to ensure pin accessibility and achieve 0 DRC violations. Fixes The-OpenROAD-Project#4478 Signed-off-by: Bandham Balaji <bandhambalaji@gmail.com>
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Code Review
This pull request updates the configuration for the coralnpu design on the asap7 platform by introducing three new environment variables: PLACE_DENSITY_LB_ADDON, CELL_PAD_IN_SITES_GLOBAL_PLACEMENT, and CELL_PAD_IN_SITES_DETAIL_PLACEMENT. These additions configure placement density and cell padding parameters. There are no review comments, and I have no feedback to provide.
🔍 QoR checkMetrics reflect the PR merge build — i.e. what will land on the target branch. Commit 62 design(s) checked — 0 with regression(s), 0 without a comparable baseline. |
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@eder-matheus This PR directly resolves issue #4478 by adding PLACE_DENSITY_LB_ADDON = 0.20 and horizontal cell padding (CELL_PAD_IN_SITES = 1) to �sap7/coralnpu, eliminating the pin-access shorts and achieving 0 DRC violations. All Jenkins CI tests (Build #1) have passed cleanly across 62/62 designs with 0 regressions. The PR is clean and ready for review whenever convenient. Thanks! |
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Summary
This PR fixes Issue #4478 ("Asap7 coralnpu with lower CORE_UTILIZATION gets 'stuck' in DRT").
Root Cause
When
CORE_UTILIZATIONwas set to55(or lower),PLACE_DENSITYwas unconstrained inflow/designs/asap7/coralnpu/config.mkand fell back to the platform default0.60. Because placement density (0.60) was higher than core utilization (0.55), standard cells were packed into dense clusters with 0 horizontal cell padding (CELL_PAD_IN_SITES = 0) adjacent tofakerammacro channels (RTLMP_MIN_CHANNEL_SIZE = 4 4).During detailed routing, TritonRoute was unable to resolve pin access for standard cell pins on M1/M2 at
core.score/regfile, resulting in persistent Metal 2 shorts and Metal 3 VDD spacing violations.Fix
In
flow/designs/asap7/coralnpu/config.mk:export PLACE_DENSITY_LB_ADDON = 0.20, allowing placement density to dynamically track lower-bound core utilization (consistent withasap7/ibexandasap7/swerv_wrapper).export CELL_PAD_IN_SITES_GLOBAL_PLACEMENT = 1export CELL_PAD_IN_SITES_DETAIL_PLACEMENT = 1Verification Results
Tested on
asap7/coralnpuwithCORE_UTILIZATION=55:3_place.odb): Legalized cleanly with cell padding intact.4_cts.odb): Passed formal logic equivalence check (4_rsz_lecclean).5_1_grt.odb): FastRoute completed with 0 overflow.5_2_route.odb): Converged cleanly in 11 optimization iterations to 0 DRC errors (detailedroute__route__drc_errors: 0).5_route_drc.rpt): 0 violations (0 bytes).Fixes #4478