Add support for Apple's vendor-specific aarch64 instructions#8316
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The following instructions are disassembled and lifted to intrinsics: * `genter #imm5` * `gexit` * `sdsb <domain>` * `wkdmc <Xd>, <Xs>` * `wkdmd <Xd>, <Xs>` * `at_as1elx <Xt>` * `mul53lo <Vd>.2d, <Vm>.2d` * `mul53hi <Vd>.2d, <Vm>.2d` Additionally, AMX instructions are disassembled but not yet lifted. Fixes #5933. These instructions are in encoding space that is unallocated by ARM. As we do not currently have any mechanism for architecture variants (#979) and these encodings are not currently used by any other vendor, I've opted to have `Arm64Architecture` decode these unconditionally. In hopes of a better future, I've structured the code such that the vendor-specific instruction handling is entirely separate from the primary disassembler / lifting logic. When support for architecture variants is added in the future, this logic can all be moved into an Apple-specific variant.
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The following instructions are disassembled and lifted to intrinsics:
genter #imm5gexitsdsb <domain>wkdmc <Xd>, <Xs>wkdmd <Xd>, <Xs>at_as1elx <Xt>mul53lo <Vd>.2d, <Vm>.2dmul53hi <Vd>.2d, <Vm>.2dAdditionally, AMX instructions are disassembled but not yet lifted.
Fixes #5933.
These instructions are in encoding space that is unallocated by ARM. As we do not currently have any mechanism for architecture variants (#979) and these encodings are not currently used by any other vendor, I've opted to have
Arm64Architecturedecode these unconditionally.In hopes of a better future, I've structured the code such that the vendor-specific instruction handling is entirely separate from the primary disassembler / lifting logic. When support for architecture variants is added in the future, this logic can all be moved into an Apple-specific variant.