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sched/spinlock: Refactor critical section implementation with rspinlock foundation and SMP optimization#18135

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hujun260 wants to merge 8 commits intoapache:masterfrom
hujun260:apache_remove_csection
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sched/spinlock: Refactor critical section implementation with rspinlock foundation and SMP optimization#18135
hujun260 wants to merge 8 commits intoapache:masterfrom
hujun260:apache_remove_csection

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@hujun260 hujun260 commented Jan 24, 2026

Summary

This pull request refactors the NuttX critical section implementation to use rspinlock_t as the unified foundation while optimizing performance for both SMP and non-SMP configurations. The series introduces enhanced spinlock operations, consolidates the scheduler interface, and eliminates deprecated synchronization mechanisms.

should merge after apache/nuttx-apps#3375

Changes Made

  1. Critical Section Refactoring - Standardize interface naming, remove redundant declarations, and consolidate SMP/non-SMP code paths for improved maintainability and reduced compilation complexity.

  2. Performance Optimization - Optimize critical section scope by narrowing protection windows to essential operations only, reducing interrupt latency and improving system responsiveness.

  3. Architecture Consolidation - Replace up_switch_context with unified nxsched_switch interface across all architecture implementations for improved consistency and reduced code duplication.

  4. Cleanup and Removal - Remove deprecated irqcount field and unnecessary preprocessor directives, simplifying the TCB structure and reducing memory overhead.

TEST

OSTEST pass

@github-actions github-actions bot added Area: Tooling Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: simulator Issues related to the SIMulator Arch: sparc Issues related to the SPARC architecture Arch: x86_64 Issues related to the x86_64 architecture Arch: xtensa Issues related to the Xtensa architecture Area: Drivers Drivers issues Area: File System File System issues Area: OS Components OS Components issues Area: USB Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces. labels Jan 24, 2026
@hujun260 hujun260 force-pushed the apache_remove_csection branch from 4e30316 to 3435fb0 Compare January 24, 2026 09:04
@hujun260 hujun260 force-pushed the apache_remove_csection branch 8 times, most recently from f2e017a to 027169c Compare February 1, 2026 05:11
@github-actions github-actions bot added the Area: Sensors Sensors issues label Feb 1, 2026
@hujun260 hujun260 force-pushed the apache_remove_csection branch 9 times, most recently from 4b4d2ba to 9bb5a7a Compare February 3, 2026 07:02
Remove unnecessary preprocessor #undef directives to improve code
clarity and reduce conditional compilation complexity. This cleanup
aligns with the refactored critical section interface.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
Consolidate architecture-specific context switching by replacing
up_switch_context with unified nxsched_switch interface, reducing
code duplication and improving scheduler integration consistency
across all architecture implementations.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
Optimize critical section usage by reducing protection scope to only
cover essential operations, improving system responsiveness and
reducing interrupt latency while maintaining synchronization safety.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
Refactor critical section implementation to use rspinlock_t as the
foundation, providing consistent synchronization semantics across SMP
and non-SMP configurations with improved nesting support and reduced
overhead.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
Clean up and remove the deprecated irqcount field from task structures
as it is no longer used by the refactored critical section implementation.
This simplifies the TCB structure and reduces memory overhead.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
Inline enter_critical_section function calls in performance-critical
paths to reduce function call overhead while maintaining consistent
semantics, improving overall system latency and responsiveness in
real-time scenarios.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
Optimize critical section implementation for non-SMP configurations by
directly using up_irq_save/restore instead of rspinlock operations,
reducing context switch overhead while maintaining compatibility with
SMP code paths.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
@hujun260 hujun260 force-pushed the apache_remove_csection branch from 9bb5a7a to e10bf58 Compare February 3, 2026 10:29
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please split the PR in multple PRs that can be understood and reviewed

1.Critical Section Refactoring - Standardize interface naming, remove redundant declarations, and consolidate SMP/non-SMP code paths for improved maintainability and reduced compilation complexity.

2.Performance Optimization - Optimize critical section scope by narrowing protection windows to essential operations only, reducing interrupt latency and improving system responsiveness.

3.Architecture Consolidation - Replace up_switch_context with unified nxsched_switch interface across all architecture implementations for improved consistency and reduced code duplication.

4.Cleanup and Removal - Remove deprecated irqcount field and unnecessary preprocessor directives, simplifying the TCB structure and reducing memory overhead.

Add #include <nuttx/spinlock.h> to source files across avr, mips,
renesas, and sparc architectures that use irqstate_t and critical
section functions but were missing the required header file.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
@hujun260 hujun260 force-pushed the apache_remove_csection branch from e10bf58 to b94ef26 Compare February 3, 2026 13:46
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Labels

Arch: arm Issues related to ARM (32-bit) architecture Arch: arm64 Issues related to ARM64 (64-bit) architecture Arch: avr Issues related to all AVR(8-bit or 32-bit) architectures Arch: mips Issues related to the MIPS architecture Arch: renesas Issues related to the Renesas chips Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Arch: simulator Issues related to the SIMulator Arch: sparc Issues related to the SPARC architecture Arch: x86_64 Issues related to the x86_64 architecture Arch: xtensa Issues related to the Xtensa architecture Area: Audio Area: Drivers Drivers issues Area: File System File System issues Area: Networking Effects networking subsystem Area: OS Components OS Components issues Area: Sensors Sensors issues Area: Tooling Area: USB Area: Video Board: arm Board: mips Board: risc-v Board: xtensa Size: L The size of the change in this PR is large Size: M The size of the change in this PR is medium Size: XL The size of the change in this PR is very large. Consider breaking down the PR into smaller pieces.

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6 participants