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JHEMCUF435: enable UART2#11597

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sensei-hacker merged 1 commit into
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dtrbinh:fix/jhemcuf435-uart2
May 31, 2026
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JHEMCUF435: enable UART2#11597
sensei-hacker merged 1 commit into
iNavFlight:maintenance-9.xfrom
dtrbinh:fix/jhemcuf435-uart2

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@dtrbinh dtrbinh commented May 28, 2026

JHEMCUF435: enable UART2

Summary

This PR enables UART2 on the JHEMCUF435 target and updates SERIAL_PORT_COUNT accordingly.

UART2 was already documented in the target file, but it was left commented out with this note:

UART2 TX does not work due currently unknown software issue

The target already contained the intended UART2 mapping:

  • UART2 RX: PB0, UART2_RX_AF 6
  • UART2 TX: PA8, UART2_TX_AF 8

This PR restores that mapping and increases SERIAL_PORT_COUNT from 8 to 9 because the target now exposes:

  • USB VCP
  • UART1
  • UART2
  • UART3
  • UART4
  • UART5
  • UART6
  • UART7
  • UART8

Rationale

The original UART2 comment appears to refer to an AT32F43x UART driver issue that has since been fixed.

Relevant history:

  • 51d98cffe added support for specifying AT32 UART RX/TX alternate functions independently.
  • In that implementation, the TX pin configuration accidentally used uart->rx_af instead of uart->tx_af.
  • This was later fixed by a941b14a8 / PR #10840 (f435 correct uart->tx_af), changing the TX configuration to use the correct uart->tx_af value.
  • JHEMCUF435AIO was then updated in 9b43222ee to use the same UART2 alternate-function mapping style:
    • UART2_RX_AF 6
    • UART2_TX_AF 8
    • UART2_RX_PIN PB0
    • UART2_TX_PIN PA8

Related target history:

  • JHEMCUF435 was added in 5283cd7c9, merged via PR #10825. This is where the commented UART2 block and the “software issue” note were introduced.
  • JHEMCUF435AIO was added via PR #10740, and later received the UART2 AF update above.

Because the current AT32F43x serial driver now correctly applies uart->tx_af to TX pins, the earlier software limitation should no longer apply.

Notes for reviewers

This PR only changes the JHEMCUF435 target configuration. It does not modify common serial driver code.

The only remaining point to verify is hardware-level confirmation that the non-AIO JHEMCUF435 board routes the TX2 pad to MCU pin PA8. The mapping itself matches the existing target comments and the related JHEMCUF435AIO configuration pattern.

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Branch Targeting Suggestion

You've targeted the master branch with this PR. Please consider if a version branch might be more appropriate:

  • maintenance-9.x - If your change is backward-compatible and won't create compatibility issues between INAV firmware and Configurator 9.x versions. This will allow your PR to be included in the next 9.x release.

  • maintenance-10.x - If your change introduces compatibility requirements between firmware and configurator that would break 9.x compatibility. This is for PRs which will be included in INAV 10.x

If master is the correct target for this change, no action is needed.


This is an automated suggestion to help route contributions to the appropriate branch.

@dtrbinh dtrbinh changed the base branch from master to maintenance-9.x May 28, 2026 05:34
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Thanks for the detailed description and history!

Have you tested it with the hardware? My description of #10840 suggests I may have tested it with this board, but forgot to update the target file.

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Test firmware build ready — commit 7884f4b

Download firmware for PR #11597

1 targets built. Find your board's .hex file by name on that page (e.g. MATEKF405SE.hex). Files are individually downloadable — no GitHub login required.

Development build for testing only. Use Full Chip Erase when flashing.

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dtrbinh commented May 28, 2026

Thanks for the detailed description and history!

Have you tested it with the hardware? My description of #10840 suggests I may have tested it with this board, but forgot to update the target file.

@sensei-hacker yes it works well. Sorry for late response.

IMG_3732
9e6c1ba4-acdc-44ca-a96b-58c30ab7bac7.mp4

@sensei-hacker sensei-hacker merged commit 871bb55 into iNavFlight:maintenance-9.x May 31, 2026
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