LLVM and SPIRV-LLVM-Translator pulldown (WW52 2025) #20968
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/usr/bin/ld: tools/clang/unittests/Analysis/Scalable/CMakeFiles/ClangSca lableAnalysisFrameworkTests.dir/ASTEntityMappingTest.cpp.o: undefined re ference to symbol '_ZN5clang7ASTUnitD1Ev
…167754) This adjusts the behavior of running dap_server.py directly to better support the current state of development. A few parts of the 'main' body were stale and not functional. These improvements include: * Instead of the custom tracefile / replay file parsing logic, I adjusted the replay helper to handle parsing lldb-dap log files created with the `LLDBDAP_LOG` env variable, allowing you to more easily run a failing test like: `python3 lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py --adapter lldb-dap -r lldb-test-build.noindex/tools/lldb-dap/console/TestDAP_console.test_custom_escape_prefix/dap.txt` * Migrated argument parsing to `argparse`, that is in all verisons of py3+ and has a few improvements over `optparse`. * Corrected the existing arguments and updated `run_vscode` > `run_adapter`. You can use this for simple debugging like: `xcrun python3 lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py --adapter=lldb-dap --adapter-arg='--pre-init-command' --adapter-arg 'help' --program a.out --init-command 'help'`
Adds a flag COMPILER_RT_PROFILE_BAREMETAL, which disables the parts of the profile runtime which require a filesystem or malloc. This minimal library only requires string.h from the C library. This is useful for profiling or code coverage of baremetal images, which don't have filesystem APIs, and might not have malloc configured (or have limited heap space). Expected usage: - Add code to your project to call `__llvm_profile_get_size_for_buffer()` and `__llvm_profile_write_buffer()` to write the profile data to a buffer in memory, and then copy that data off the device using target-specific tools. - If you're using a linker script, set up your linker script to map the profiling and coverage input sections to corresponding output sections with the same name, and mark them KEEP. `__llvm_covfun` and `__llvm_covmap` are non-allocatable, `__llvm_prf_names` is read-only allocatable, and `__llvm_prf_cnts` and `__llvm_prf_data` are read-write allocatable. - The resulting data is in same format as the non-baremetal profiles. There's some room for improvement here in the future for doing profiling and code coverage for baremetal. If we revised the profiling format, and introduced some additional host tooling, we could move some of the metadata into non-allocated sections, and construct the profraw file on the host. But this patch is sufficient for some use-cases.
Use the same twiden format for PseudoSF_VSETTM and PseudoSF_VSETTK as other XSfmm pseudos. Though I don't think we use the operand from these instructions.
… peelToTurnInvariantLoadsDereferenceable. (#171547) llvm.assume intrinsics have the mayWriteToMemory property, but won't prevent the load from becoming dereferenceable.
Add documentation for variadic `isa<>` in the LLVM Programmer's Manual.
…ge (#171705) As it is done in `flang-rt/lib/runtime/edit-input.cpp`, emit a runtime error message when trying to raise IEEE exception on the device. `MapException` and `feraiseexcept` are used in the lowering of the nearest intrinsic even on the device.
…utable in popen.cpp" (#171706) Reverts llvm/llvm-project#171622 Co-authored-by: Andrew Haberlandt <[email protected]>
Previously we would hit an assertion failure when a relocation represented by a PAuth ifunc required a GOT and the addend of a relocation did not fit into the immediate operand of an ADD instruction. Fix it by extracting a function for materializing arbitrary addends and using it to materialize the addend. Reviewers: fmayer, hvdijk Pull Request: llvm/llvm-project#171707
Previously we would assert when a ValueTypeByHwMode was missing a case for the current mode, now we report an error instead. Interestingly this error only ocurrs when the DAG patterns use RegClassByHwMode, but not normal RegisterClass instances. Found while I added RegClassByHwMode to RISC-V and was getting an assertion due to `XLenFVT`/`XLenVecI32VT` not having an entry for the default mode. Reviewed By: arsenm Pull Request: llvm/llvm-project#171254
Previously, we were emitting a broken AliasPatternCond array, outputting `MyTarget::RegClassByHwModeRegClassID` which does not exist. Instead, we now add a new predicate and pass the RegClassByHwMode index as the value argument. Pull Request: llvm/llvm-project#171264
Reviewers: jvoung Reviewed By: jvoung Pull Request: llvm/llvm-project#170947
printFlags takes care of inserting the correct amount of spaces, depending on whether there are flags to print or not.
This pass implements the OpenACC loop tiling transformation for acc.loop
operations that have the tile clause (OpenACC 3.4 spec, section 2.9.8).
The tile clause specifies that the iterations of the associated loops
should be divided into tiles (rectangular blocks). The pass transforms a
single or nested acc.loop with tile clauses into a structure of "tile
loops" (iterating over tiles) containing "element loops" (iterating
within tiles).
For example, tiling a 2-level nested loop with tile(T1, T2):
```
// Before tiling:
acc.loop tile(T1, T2) control(%i, %j) = ...
// After tiling:
acc.loop control(%i) step (s1*T1) { // tile loop 1
acc.loop control(%j) step (s2*T2) { // tile loop 2
acc.loop control(%ii) = (%i) to (min(ub1, %i+s1*T1)) {
acc.loop control(%jj) = (%j) to (min(ub2, %j+s2*T2)) {
// loop body using %ii, %jj
}
}
}
}
```
Key features:
- Handles constant tile sizes and wildcard tile sizes ('*') which use a
configurable default tile size
- Properly handles collapsed loops with tile counts exceeding collapse
count by uncollapsing loops before tiling
- Distributes gang/worker/vector attributes appropriately: gang -> tile
loops, vector -> element loops
- Validates that tile size types are not wider than loop IV types
- Emits optimization remarks for tiling decisions
Three test files are added:
- acc-loop-tiling.mlir: Tests single and nested loop tiling with
constant tile sizes, unknown tile sizes (*), and loops with collapse
attributes
- acc-loop-tiling-invalid.mlir: Tests error diagnostic when tile size
type is wider than the loop IV type
- acc-loop-tiling-remarks.mlir: Tests optimization remarks emitted for
tiling decisions including default tile size selection
Co-authored-by: Vijay Kandiah <[email protected]>
Reviewers: jvoung Reviewed By: jvoung Pull Request: llvm/llvm-project#170950
llvm/llvm-project#169131 Should fix: ASTEntityMappingTest.cpp.o: undefined reference to symbol '_ZN4llvm3omp27isAllowedClauseForDirectiveENS0_9DirectiveENS0_6ClauseEj' https://lab.llvm.org/buildbot/#/builders/10/builds/18851
That hopefully concludes the initial upstreaming. Reviewers: jvoung Reviewed By: jvoung Pull Request: llvm/llvm-project#170951
… (#169779) SelectionDAG uses the DAGCombiner to fold a load followed by a sext to a load and sext instruction. For example, in x86 we will see that ``` %1 = load i32, ptr @GloBaRR #dbg_value(i32 %1, !43, !DIExpression(), !52) %2 = sext i32 %1 to i64, !dbg !53 ``` is converted to: ``` %0:gr64_nosp = MOVSX64rm32 $rip, 1, $noreg, @GloBaRR, $noreg, debug-instr-number 1, debug-location !51 DBG_VALUE $noreg, $noreg, !"Idx", !DIExpression(), debug-location !52 ``` The `DBG_VALUE` needs to be transferred correctly to the new combined instruction, and it needs to be appended with a `DIExpression` which contains a `DW_OP_LLVM_fragment`, describing that the lower bits of the virtual register contain the value. This patch fixes the above described problem.
This patch fixes issues introduced by llvm/llvm-project#171491 when running tests in CI. The shell tests expect certain characters when matching diagnostics. With llvm/llvm-project#171491, those characters can either be Unicode specific characters or their ASCII equivalent. The tests were always expecting the ASCII version. This patch fixes this by using a regex to match one or the other.
If the 'counted_by' value is signed, we will incorrectly allow accesses when the value is negative. This has obvious bad effects as it will allow accessing a huge swath of unallocated memory. Also clarify and rearrange the parameters to make them more perspicuous. Fixes: #170987.
In order to allow arm64 code to run on MTE environments, we need to make the compiler only assume the top 4 bits can be ignored as MTE occupies the lower 4. rdar://164645323
This commit leaves "b" aliased to the old _regexp-break for now. The two variants are identical except that `_regexp-break` allows you to say: `(lldb) b <unrecognized_input> ` which gets translated to: `break set <unrecognized_input> ` So switching people to `_regexp-break-add` would be a surprising behavior change. It would be wrong for `_regexp_break-add` have one branch that call `break set`, so to avoid surprise, I'll add the command and let people who are playing with `break add` instead of `break set` can set the alias to the new one by hand for now.
Having duplicate mode entries previously asserted (or silently replaced the last value with a new one in release builds). Report an error with a helpful message instead. Pull Request: llvm/llvm-project#171715
I have a change to validate the operand classes emitted in the AsmParser and that caused llvm/test/MC/RISCV/rv32p-valid.s to fail due to the rd_wb register using a different register class from rd: `PWADDA_H operand 1 register X6 is not a member of register class GPRPair` This happens because tablegen's AsmMatcherEmitter emits code to literally copy over the tied registers and does not feed them through the equivalent of RISCVAsmParser::validateTargetOperandClass() which would allow adjusting these operand classes. Ideally we would handle this in tablegen (or at least add an error), but the tied operand handling logic is rather complex and I don't understand it yet. For now just update the rd register class to match rd_wb. Pull Request: llvm/llvm-project#171738
…ision_integers rename
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This is ready for review.
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/merge |
bb-sycl
approved these changes
Jan 5, 2026
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Mon 05 Jan 2026 04:44:12 PM UTC --- Start to merge the commit into sycl branch. It will take several minutes. |
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Merge 1st, @intel/dpcpp-spirv-reviewers Please do post-commit review and follow up. Thanks! |
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Mon 05 Jan 2026 04:51:28 PM UTC --- Merge the branch in this PR to base automatically. Will close the PR later. |
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LLVM: llvm/llvm-project@b123b70
SPIRV-LLVM-Translator: KhronosGroup/SPIRV-LLVM-Translator@199d2e027d650a5