Add LSC-1 Tiny Tapeout ttsky26c integration lane

[Th0rgal]

Summary

• add a uniquely named tt_um_* ttsky26c wrapper around the unchanged asic_core/ LSC-1 boundary
• explicitly map the 8-bit request/response ready-valid lane and safely clamp/disable every output while ena is low
• add honest yaml_version 6 metadata, a conservative but unproven 2x2 candidate, LibreLane config, cocotb RTL/GL tests, and ttsky26c GDS/precheck/gl_test/viewer workflows
• document source boundaries, pin ownership, local evidence, and unresolved physical-design claims

Immutable base

• commit: fda85f5efc6f5b460d72204b4d9c0d882960ec29
• tree: df42a6211828d856e9a21ba61ecc2cd1b9dc4e71
• asic_core/ diff from base: empty

Local PASS evidence

• Icarus SystemVerilog elaboration: exit 0
• Yosys hierarchy/proc/check: exit 0
• make -C test cocotb Tiny Tapeout lane test: exit 0
• make check: exit 0
• make sim: exit 0
• tt_tool.py --create-user-config: exit 0
• make checksum-check: exit 0

Unresolved / authoritative CI

• local make lean: exit 2; real Lake binary unavailable
• local make formal: exit 2; sby unavailable
• local tt_tool.py --harden: exit 1 before physical design; LibreLane module unavailable and PDK_ROOT unset
• GDS, precheck, DRC/LVS, gate-level simulation, timing, area/tile fit, and PPA are not claimed
• the real TinyTapeout/tt-gds-action@ttsky26c jobs on this draft PR are the authoritative external attempt

This PR does not claim ASIC readiness and must not be merged based only on RTL results.

---

Note

Medium Risk
Touches tapeout metadata, active CI top, and new formal boundaries for retained arithmetic; physical signoff still depends on external GDS/GL jobs, and the profile is not interchangeable with full LSC-1 host packet logic.

Overview
Adds the LSC-1µ (LSC-1 Micro) Tiny Tapeout lane as a deliberately smaller sub-core: streamed byte opcodes for GF(2¹²⁸) XOR/MUL/SET only, with info.yaml now targeting tt_um_lfglabs_lsc1u on a 1×2 tile and a minimal RTL closure (lsc1u_core plus reused multiplier blocks). Full lean_silicon_lsc1 in asic_core/ stays the FPGA/larger-ASIC boundary; a separate tt_um_lfglabs_lean_silicon_lsc1 wrapper remains for the canonical top without changing that RTL.

Verification and CI expand around the new profile: unbounded lsc1u_protocol and cover-based lsc1u_reachability formal harnesses (multiplier over-approximated where control does not depend on product), formal-mutations / check_mutations.py in CI, a Python lsc1u_model oracle with unit tests, and cocotb RTL/GL tests (Makefile.tt, test_tt.py, power-pin fixes for Icarus GL). New workflows run GDS/precheck/gl_test/viewer and a dedicated Tiny Tapeout RTL test job; consistency tools and docs (LSC1U_ARCHITECTURE.md, TINY_TAPEOUT_TTSKY26C.md) describe pins, exclusions, and evidence-driven tile sizing—not a claim that full LSC-1 packet execution is on silicon.

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[chatgpt-codex-connector]

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[chatgpt-codex-connector]

Point the tapeout guide at the active LSC-1u top

Update this guide to name tt_um_lfglabs_lsc1u: the reviewed info.yaml and src/user_config.tcl both select that reduced profile, while tt_um_lfglabs_lean_silicon_lsc1 is an orphan full-core wrapper excluded from the declared source list. As written, anyone using this document to inspect or reproduce the ttsky26c integration is directed to a different design with a different protocol and source boundary.

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