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fixes #156782

: F16<0b1001010111001000, (outs), (ins), "lpm", []>,
Requires<[HasLPM]>;
let isReMaterializable = 1, mayLoad = 1, hasSideEffects = 0 in {
let Defs = [R0], Uses = [R31R30] in
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@Patryk27 Patryk27 Dec 22, 2025

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Now that i think about it, why do we have Defs = [R0] here? 🤔


// These pseudo instructions are combination of the OUT and ELPM instructions.
let Defs = [R0] in {
let Defs = [R0], hasSideEffects = 1 in {
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@Patryk27 Patryk27 Dec 22, 2025

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ELPMBRdZ gets expanded to OUTARr + ELPMRdZ / ELPM that don't have hasSideEffects = 1 themselves, so this feels inconsistent 🤔

it seems that either those instructions should be marked as hasSideEffects or this instruction shouldn't have this annotation

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(i imagine OUTARr should be the one marked hasSideEffects = 1?)

Uses = [R31R30] in def LPM
: F16<0b1001010111001000, (outs), (ins), "lpm", []>,
Requires<[HasLPM]>;
let isReMaterializable = 1, mayLoad = 1, hasSideEffects = 0 in {
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@Patryk27 Patryk27 Dec 22, 2025

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Inside this block we've also got LPMRdZPi and LPMWRdZPi that I think are not rematerializable, because they increment the Z register.

//
// This instruction may be removed once PR13375 is fixed.
let mayLoad = 1, hasSideEffects = 0 in
let hasSideEffects = 0 in
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@Patryk27 Patryk27 Dec 22, 2025

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Since we're touching the code, it'd be nice to mark all instructions appropriately at once (add hasSideEffects = 0/1) - this seems to be what e.g. RISC-V is doing.

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[AVR] Make a careful check on flags of load/store instructions

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