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Pull requests: pulp-platform/tech_cells_generic

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Pull requests list

Map tc_clk_gating to FPGA primitive for Xilinx FPGAs
#38 opened Oct 1, 2025 by LucaRufer Loading…
1
[HW] Add tc_latch_enpos_rstn
#36 opened Sep 15, 2025 by Scheremo Loading…
1
tc_clk_xilinx.sv: Add IS_FUNCTIONAL parameter on clk_mux
#28 opened Jul 4, 2023 by CyrilKoe Contributor Loading…
@niwis
9
Padfunctional module with PU/PD signal control
#18 opened Nov 5, 2021 by mattsini1 Loading…
6
ProTip! Updated in the last three days: updated:>2026-04-07.